component
CS817x20HS
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CS817x20HS
Chipanalog · Digital Isolators · SOIC-8
CS817x20HS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for side 1, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND1. |
| 2 | INA | input | Digital input A on side 1 (corresponds to output OUTA on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V. |
| 3 | INB | input | Digital input B on side 1 (corresponds to output OUTB on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V. |
| 4 | GND1 | power_in | Ground reference for side 1, the isolated ground for the side 1 supply and inputs. |
| 5 | GND2 | power_in | Ground reference for side 2, the isolated ground for the side 2 supply and outputs, which must not be connected to GND1 as this defeats the isolation. |
| 6 | OUTB | output | Digital output B on side 2, the logic output for input INB on side 1; the default state is high for HS devices when the input is unpowered or open. |
| 7 | OUTA | output | Digital output A on side 2, the logic output for input INA on side 1; the default state is high for HS devices when the input is unpowered or open. |
| 8 | VDD2 | power_in | Power supply for side 2, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level Output Voltage | VOH | 4.7 | V | VDD1=VDD2=5V±10%, TA -40 to 105°C; IOH = -4mA | 7 | ||
| Low-level Output Voltage | VOL | 0.3 | 0.4 | V | VDD1=VDD2=5V±10%, TA -40 to 105°C; IOL = 4mA | 7 | |
| Common-mode Transient Immunity | CMTI | 100 | 150 | kV/µs | VDD1=VDD2=5V±10%; VI = VDDI1 or 0 V, VCM = 1500 V | 7 | |
| High-Level Input Leakage Current | IIH | 1 | µA | VDD1=VDD2=5V±10%; VIH = VDDI at INx | 7 | ||
| Low-Level Input Leakage Current | IIL | -1 | µA | VDD1=VDD2=5V±10%; VIL = 0 V at INx | 7 | ||
| High-level Output Voltage | VOH | 3 | V | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; IOH = -4mA | 7 | ||
| High-level Output Voltage | VOH | 2.2 | V | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; IOH = -4mA | 7 | ||
| Low-level Output Voltage | VOL | 0.2 | 0.4 | V | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; IOL = 4mA | 7 | |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | 30 | 60 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 | |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | 170 | 340 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 | |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | 40 | 80 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 | |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | 170 | 340 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 | |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | 45 | 90 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 | |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | 180 | 360 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 | |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | 180 | 360 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 | |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | 300 | 600 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 | |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | 25 | 50 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 | |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | 155 | 310 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 | |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | 30 | 60 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 | |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | 160 | 320 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 | |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | 35 | 70 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 | |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | 165 | 330 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 | |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | 115 | 230 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 | |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | 235 | 470 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 | |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | 25 | 50 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 9 | |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | 150 | 300 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 9 | |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | 35 | 70 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 9 | |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | 155 | 310 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 9 | |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | 30 | 60 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 | |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | 155 | 310 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 | |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | 40 | 80 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 | |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | 180 | 360 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 | |
| Data Rate | DR | 0 | 200 | kbps | VDD1=VDD2=2.5V~5.5V, TA -40 to 105°C | 9 | |
| Propagation Delay Time | tPLH, tPHL | 1.1 | 2 | µs | 9 | ||
| Pulse Width Distortion | PWD | 100 | ns | /tPLH - tPHL/ | 9 | ||
| Channel-to-Channel Output Skew Time | tsk(o) | 100 | ns | Same-direction channels | 9 | ||
| Output Signal Rise Time | tr | 2.8 | 5 | ns | 9 | ||
| Output Signal Fall Time | tf | 2.8 | 5 | ns | 9 | ||
| Default Output Delay Time from Input Power Loss | tDO | 400 | 600 | µs | 9 | ||
| Supply Voltage on Side 1 and 2 | VDD1, VDD2 | 2.375 | 5.5 | V | 5 | ||
| High-level Output Current | IOH | 4 | mA | VDDO1 = 5V | 5 | ||
| High-level Output Current | IOH | 2 | mA | VDDO = 3.3V | 5 | ||
| High-level Output Current | IOH | 1 | mA | VDDO = 2.5V | 5 | ||
| Low-level Output Current | IOL | -4 | mA | VDDO = 5V | 5 | ||
| Low-level Output Current | IOL | -2 | mA | VDDO = 3.3V | 5 | ||
| Low-level Output Current | IOL | -1 | mA | VDDO = 2.5V | 5 | ||
| Ambient Temperature | TA | -40 | 25 | 125 | °C | 5 | |
| Power Supply Voltage | VDD1, VDD2 | -0.5 | 6 | V | VDD1, VDD2 power supply voltage; peak, with respect to local ground | 5 | |
| Voltage at INX, OUTX | Vin | -0.5 | V | Voltage at INX, OUTX; upper limit printed as VDDI+0.5 | 5 | ||
| Output Current | IO | -20 | 20 | mA | 5 | ||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| Junction-to-ambient Thermal Resistance | RθJA | 110.1 | °C/W | SOIC8-NB(S) package | 5 |
CAD (KiCad official)
- Symbol:
CS817x20HS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cs817x20hs-etched.step/cs817x20hs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs817x20hs.step/cs817x20hs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (20 pp, sha256
370cfd8ae67fb372, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CS817x20HS
**Chipanalog** · Digital Isolators · SOIC-8
CS817x20HS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for side 1, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND1. |
| 2 | INA | input | Digital input A on side 1 (corresponds to output OUTA on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V. |
| 3 | INB | input | Digital input B on side 1 (corresponds to output OUTB on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V. |
| 4 | GND1 | power_in | Ground reference for side 1, the isolated ground for the side 1 supply and inputs. |
| 5 | GND2 | power_in | Ground reference for side 2, the isolated ground for the side 2 supply and outputs, which must not be connected to GND1 as this defeats the isolation. |
| 6 | OUTB | output | Digital output B on side 2, the logic output for input INB on side 1; the default state is high for HS devices when the input is unpowered or open. |
| 7 | OUTA | output | Digital output A on side 2, the logic output for input INA on side 1; the default state is high for HS devices when the input is unpowered or open. |
| 8 | VDD2 | power_in | Power supply for side 2, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND2. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level Output Voltage | VOH | | | 4.7 | V | VDD1=VDD2=5V±10%, TA -40 to 105°C; IOH = -4mA | 7 |
| Low-level Output Voltage | VOL | | 0.3 | 0.4 | V | VDD1=VDD2=5V±10%, TA -40 to 105°C; IOL = 4mA | 7 |
| Common-mode Transient Immunity | CMTI | 100 | 150 | | kV/µs | VDD1=VDD2=5V±10%; VI = VDDI1 or 0 V, VCM = 1500 V | 7 |
| High-Level Input Leakage Current | IIH | | | 1 | µA | VDD1=VDD2=5V±10%; VIH = VDDI at INx | 7 |
| Low-Level Input Leakage Current | IIL | -1 | | | µA | VDD1=VDD2=5V±10%; VIL = 0 V at INx | 7 |
| High-level Output Voltage | VOH | | | 3 | V | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; IOH = -4mA | 7 |
| High-level Output Voltage | VOH | | | 2.2 | V | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; IOH = -4mA | 7 |
| Low-level Output Voltage | VOL | | 0.2 | 0.4 | V | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; IOL = 4mA | 7 |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | | 30 | 60 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | | 170 | 340 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | | 40 | 80 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | | 170 | 340 | µA | VDD1=VDD2=5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | | 45 | 90 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | | 180 | 360 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | | 180 | 360 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | | 300 | 600 | µA | VDD1=VDD2=5V±10%; all channels switching 50% duty square wave, 5.0V input, CL=15 pF per channel | 8 |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | | 25 | 50 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | | 155 | 310 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 8 |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | | 30 | 60 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | | 160 | 320 | µA | VDD1=VDD2=3.3V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 8 |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | | 35 | 70 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | | 165 | 330 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | | 115 | 230 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | | 235 | 470 | µA | VDD1=VDD2=3.3V±10%; all channels switching 50% duty square wave, 3.3V input, CL=15 pF per channel | 8 |
| Supply Current side 1, DC signal (VIN=VDDI1, HS) | IDD1 | | 25 | 50 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 9 |
| Supply Current side 2, DC signal (VIN=VDDI1, HS) | IDD2 | | 150 | 300 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = VDDI1 (CS817x20HS), DC signal | 9 |
| Supply Current side 1, DC signal (VIN=0V, HS) | IDD1 | | 35 | 70 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 9 |
| Supply Current side 2, DC signal (VIN=0V, HS) | IDD2 | | 155 | 310 | µA | VDD1=VDD2=2.5V±10%, TA -40 to 105°C; VIN = 0V (CS817x20HS), DC signal | 9 |
| Supply Current side 1, AC signal 10kbps (5kHz) | IDD1 | | 30 | 60 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 |
| Supply Current side 2, AC signal 10kbps (5kHz) | IDD2 | | 155 | 310 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 |
| Supply Current side 1, AC signal 200kbps (100kHz) | IDD1 | | 40 | 80 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 |
| Supply Current side 2, AC signal 200kbps (100kHz) | IDD2 | | 180 | 360 | µA | VDD1=VDD2=2.5V±10%; all channels switching 50% duty square wave, 2.5V input, CL=15 pF per channel | 9 |
| Data Rate | DR | 0 | | 200 | kbps | VDD1=VDD2=2.5V~5.5V, TA -40 to 105°C | 9 |
| Propagation Delay Time | tPLH, tPHL | | 1.1 | 2 | µs | | 9 |
| Pulse Width Distortion | PWD | | | 100 | ns | /tPLH - tPHL/ | 9 |
| Channel-to-Channel Output Skew Time | tsk(o) | | | 100 | ns | Same-direction channels | 9 |
| Output Signal Rise Time | tr | | 2.8 | 5 | ns | | 9 |
| Output Signal Fall Time | tf | | 2.8 | 5 | ns | | 9 |
| Default Output Delay Time from Input Power Loss | tDO | | 400 | 600 | µs | | 9 |
| Supply Voltage on Side 1 and 2 | VDD1, VDD2 | 2.375 | | 5.5 | V | | 5 |
| High-level Output Current | IOH | | | 4 | mA | VDDO1 = 5V | 5 |
| High-level Output Current | IOH | | | 2 | mA | VDDO = 3.3V | 5 |
| High-level Output Current | IOH | | | 1 | mA | VDDO = 2.5V | 5 |
| Low-level Output Current | IOL | -4 | | | mA | VDDO = 5V | 5 |
| Low-level Output Current | IOL | -2 | | | mA | VDDO = 3.3V | 5 |
| Low-level Output Current | IOL | -1 | | | mA | VDDO = 2.5V | 5 |
| Ambient Temperature | TA | -40 | 25 | 125 | °C | | 5 |
| Power Supply Voltage | VDD1, VDD2 | -0.5 | | 6 | V | VDD1, VDD2 power supply voltage; peak, with respect to local ground | 5 |
| Voltage at INX, OUTX | Vin | -0.5 | | | V | Voltage at INX, OUTX; upper limit printed as VDDI+0.5 | 5 |
| Output Current | IO | -20 | | 20 | mA | | 5 |
| Junction Temperature | TJ | | | 150 | °C | | 5 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 5 |
| Junction-to-ambient Thermal Resistance | RθJA | | 110.1 | | °C/W | SOIC8-NB(S) package | 5 |
## CAD (KiCad official)
- Symbol: `CS817x20HS`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cs817x20hs-etched.step` / `cs817x20hs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cs817x20hs.step` / `cs817x20hs.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603003927482671104) (20 pp, sha256 `370cfd8ae67fb372`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cs817x20hs-datasheet.pdf)