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CS5381-KZZR
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Cirrus Logic Audio Interface ICs, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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{
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"type": "component",
"slug": "cs5381-kzzr",
"title": "CS5381-KZZR",
"brief": "Cirrus Logic Audio Interface ICs, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.2",
"license": "CC-BY-SA-4.0",
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"communication interface chip-uart-485-232",
"cs5381-kzzr",
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],
"component": {
"mpn": "CS5381-KZZR",
"manufacturer": "Cirrus Logic",
"package": "TSSOP-24",
"pin_count": 24,
"category": "Communication Interface Chip/UART/485/232",
"subcategory": "Audio Interface ICs",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/bdbf9d696d21962fbce4af81b809c419.pdf",
"parts": {
"symbol": "cs5381-kzzr.kicad_sym",
"footprint": "cs5381-kzzr.kicad_mod",
"model_3d": "cs5381-kzzr-hero.glb",
"model_3d_plain": "cs5381-kzzr-etched.glb",
"model_3d_step": "cs5381-kzzr-etched.step",
"model_3d_step_plain": "cs5381-kzzr.step",
"lbr": "cs5381-kzzr.lbr"
},
"distributor_links": {
"lcsc": "C5382102",
"digikey": "598-CS5381-KZZRTR-ND",
"mouser": "777-CS5381-KZZR"
},
"distributor_check": {
"checked_at": "2026-11-11T01:08:35Z",
"source": "Component Ocean /api/assign-pns",
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"status": "found"
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},
"pins": [
{
"number": "1",
"name": "RST",
"type": "input",
"description": "Reset input; the device enters a low power mode when low."
},
{
"number": "2",
"name": "M/S",
"type": "input",
"description": "Selects operation as either clock master or slave, which determines whether LRCK and SCLK are outputs or inputs."
},
{
"number": "3",
"name": "LRCK",
"type": "bidirectional",
"description": "Left/Right clock that determines which channel is active on the serial audio data line; an output equal to Fs in master mode and an input equal to Fs in slave mode."
},
{
"number": "4",
"name": "SCLK",
"type": "bidirectional",
"description": "Serial clock for the serial audio interface; an output at 64x Fs in master mode and an input (recommended 64x Fs) in slave mode."
},
{
"number": "5",
"name": "MCLK",
"type": "input",
"description": "Master clock input, the clock source for the delta-sigma modulator and digital filters."
},
{
"number": "6",
"name": "VD",
"type": "power_in",
"description": "Positive digital power supply for the digital filter section, specified 3.1 V to 5.25 V; if derived from VA through a resistor, no other logic should be driven from VD."
},
{
"number": "7",
"name": "GND",
"type": "power_in",
"description": "Ground reference; must be connected to analog ground."
},
{
"number": "8",
"name": "VL",
"type": "power_in",
"description": "Logic power supply for the digital inputs and outputs, specified 2.37 V to 5.25 V."
},
{
"number": "9",
"name": "SDOUT",
"type": "output",
"description": "Serial audio data output carrying two's complement serial audio data."
},
{
"number": "10",
"name": "MDIV",
"type": "input",
"description": "MCLK divider enable that divides the master clock by two in master mode; it must be set to logic 0 in slave mode."
},
{
"number": "11",
"name": "HPF",
"type": "input",
"description": "Digital high-pass filter enable; taking it high during normal operation freezes the stored DC offset so it can be used for system DC offset calibration."
},
{
"number": "12",
"name": "I²S/LJ",
"type": "input",
"description": "Selects the serial audio interface format, either left-justified or I²S."
},
{
"number": "13",
"name": "M0",
"type": "input",
"description": "Mode select bit 0 which, together with M1, sets the speed mode (00 single-speed, 01 double-speed, 10 quad-speed, 11 reserved)."
},
{
"number": "14",
"name": "M1",
"type": "input",
"description": "Mode select bit 1 which, together with M0, sets the speed mode (00 single-speed, 01 double-speed, 10 quad-speed, 11 reserved)."
},
{
"number": "15",
"name": "OVFL",
"type": "output",
"description": "Open-drain, active-low overflow output for both channels, requiring a 10 kΩ pull-up to VL when used and rated for a 4.0 mA maximum current sink."
},
{
"number": "16",
"name": "AINL+",
"type": "input",
"description": "Positive side of the differential left channel analog input to the delta-sigma modulator; full-scale input is 1.13*VA typical (1.07*VA to 1.18*VA) Vpp differential."
},
{
"number": "17",
"name": "AINL-",
"type": "input",
"description": "Negative side of the differential left channel analog input to the delta-sigma modulator; full-scale input is 1.13*VA typical (1.07*VA to 1.18*VA) Vpp differential."
},
{
"number": "18",
"name": "GND",
"type": "power_in",
"description": "Ground reference; must be connected to analog ground."
},
{
"number": "19",
"name": "VA",
"type": "power_in",
"description": "Positive analog power supply for the analog section, specified 4.75 V to 5.25 V (5.0 V typical)."
},
{
"number": "20",
"name": "AINR-",
"type": "input",
"description": "Negative side of the differential right channel analog input to the delta-sigma modulator; full-scale input is 1.13*VA typical (1.07*VA to 1.18*VA) Vpp differential."
},
{
"number": "21",
"name": "AINR+",
"type": "input",
"description": "Positive side of the differential right channel analog input to the delta-sigma modulator; full-scale input is 1.13*VA typical (1.07*VA to 1.18*VA) Vpp differential."
},
{
"number": "22",
"name": "VQ",
"type": "power_out",
"description": "Filter connection for the internal quiescent reference voltage, nominally 2.5 V with 25 kΩ output impedance and decoupling capacitors per the typical connection diagram."
},
{
"number": "23",
"name": "REF_GND",
"type": "power_in",
"description": "Reference ground for the internal sampling circuits; FILT+ and VQ decoupling capacitors should be placed to minimize the path from FILT+ to REFGND."
},
{
"number": "24",
"name": "FILT+",
"type": "power_out",
"description": "Positive voltage reference output for the internal sampling circuits, nominally 5 V with 4.5 kΩ output impedance, and requires external decoupling capacitance that sets low-frequency distortion."
}
],
"provenance": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin-description table lists AINL+/AINL- and AINR-/AINR+ as combined entries with pin numbers 16,; The pin table names pin 23 'REF_GND' while the package diagram prints 'REFGND'. The table name was u; The datasheet classifies VQ and FILT+ as 'Output' (reference voltage outputs). They are mapped to Ki"
],
"pages_sent": 24,
"cost_usd": 0.1069,
"at": "2026-11-11T01:08:17"
},
"datasheet": {
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"source_tier": "lcsc"
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"refuses_to_fabricate": true
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"package_dims": {
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"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
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"metadata": {
"specs": {
"Manufacturer": "Cirrus Logic",
"Package": "TSSOP-24",
"Category": "Communication Interface Chip/UART/485/232",
"Pins": "24"
},
"characteristics": {
"version": 1,
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"name": "DC Power Supplies: Analog",
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"conditions": "GND = 0 V",
"source_page": 5,
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{
"name": "DC Power Supplies: Positive Digital",
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"name": "DC Power Supplies: Digital",
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{
"name": "Digital Input Voltage (Note 3)",
"symbol": "VIND",
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"unit": "V",
"min": -0.7,
"typ": null,
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"conditions": "Max printed as VL+0.7",
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{
"name": "Ambient Operating Temperature (Power Applied)",
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{
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{
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{
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{
"name": "Gain Error",
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{
"name": "Gain Drift",
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{
"name": "Passband (-0.1 dB)",
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{
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{
"name": "Stopband Attenuation",
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{
"name": "Passband (-0.1 dB)",
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"name": "Stopband",
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{
"name": "Stopband Attenuation",
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{
"name": "Passband (-0.1 dB)",
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"conditions": "Quad-Speed Mode (100 kHz to 216 kHz sample rates)",
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{
"name": "Stopband",
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{
"name": "Stopband Attenuation",
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"typ": null,
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{
"name": "Output Sample Rate",
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"kind": "recommended_operating",
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"conditions": "Single-Speed Mode",
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{
"name": "Output Sample Rate",
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{
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{
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{
"name": "MCLK Duty Cycle",
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{
"name": "SCLK falling to LRCK transition",
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{
"name": "SCLK falling to SDOUT valid",
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{
"name": "SCLK Period",
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"typ": null,
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"conditions": "Slave Mode, Single-Speed",
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{
"name": "SCLK Period",
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"min": 72,
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"conditions": "Slave Mode, Quad-Speed",
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},
{
"name": "SDOUT valid before SCLK rising",
"symbol": "tstp",
"kind": "timing",
"unit": "ns",
"min": 10,
"typ": null,
"max": null,
"conditions": "Slave Mode, Single-Speed",
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"source": "datasheet"
},
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