component

CS5381-KZZR

Public Made by Adom

by adom

Cirrus Logic Audio Interface ICs, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232cs5381-kzzrfactory-2.0.0extractor-text

Verified CS5381-KZZR

by Ray · last 11 Nov 2026 · 2 records · files match
SymbolFootprint3D modelPins

Verification log 2 records

11 Nov 2026RayRebuilt by the parts factory: tier lcsc, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS5381-KZZR · TSSOP-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C5382102, digikey 598-CS5381-KZZRTR-ND, mouser 777-CS5381-KZZR
  • ✓family: TSSOP-24_4.4x7.8mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xzy68jui/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.21)
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 38 kB, viewers/symbol.html 19 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs5381-kzzr.kicad_sym✓ cs5381-kzzr.kicad_mod✓ cs5381-kzzr.step
9 Nov 2026RayPublished by the parts factory: tier lcsc, 24 pinsre-verified
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS5381-KZZR · TSSOP-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C5382102, digikey 598-CS5381-KZZRTR-ND, mouser 777-CS5381-KZZR
  • ✓family: TSSOP-24_4.4x7.8mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-felqy667/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.21)
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! cs5381-kzzr.kicad_sym✓ cs5381-kzzr.kicad_mod✓ cs5381-kzzr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cs5381-kzzr: viewers · Ray
cs5381-kzzr-etched.glb Publish 0.1.0 · Ray
cs5381-kzzr-etched.step cs5381-kzzr: factory component page (tier=lcsc) · Ray
cs5381-kzzr-hero.glb cs5381-kzzr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs5381-kzzr-hero.overlay.json Publish 0.1.2 · Ray
cs5381-kzzr.glb Publish 0.1.0 · Ray
cs5381-kzzr.kicad_mod Publish 0.1.0 · Ray
cs5381-kzzr.kicad_sym Publish 0.1.2 · Ray
cs5381-kzzr.lbr Publish 0.1.2 · Ray
cs5381-kzzr.step Publish 0.1.0 · Ray
package.json Publish 0.1.2 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.2 · Ray
verification.json Verified: Rebuilt by the parts factory: tier lcsc, 24 pins · Ray

CS5381-KZZR

Cirrus Logic · Audio Interface ICs · TSSOP-24

CS5381-KZZR from Cirrus Logic, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RST input Reset input; the device enters a low power mode when low.
2 M/S input Selects operation as either clock master or slave, which determines whether LRCK and SCLK are outputs or inputs.
3 LRCK bidirectional Left/Right clock that determines which channel is active on the serial audio data line; an output equal to Fs in master mode and an input equal to Fs in slave mode.
4 SCLK bidirectional Serial clock for the serial audio interface; an output at 64x Fs in master mode and an input (recommended 64x Fs) in slave mode.
5 MCLK input Master clock input, the clock source for the delta-sigma modulator and digital filters.
6 VD power_in Positive digital power supply for the digital filter section, specified 3.1 V to 5.25 V; if derived from VA through a resistor, no other logic should be driven from VD.
7 GND power_in Ground reference; must be connected to analog ground.
8 VL power_in Logic power supply for the digital inputs and outputs, specified 2.37 V to 5.25 V.
9 SDOUT output Serial audio data output carrying two's complement serial audio data.
10 MDIV input MCLK divider enable that divides the master clock by two in master mode; it must be set to logic 0 in slave mode.
11 HPF input Digital high-pass filter enable; taking it high during normal operation freezes the stored DC offset so it can be used for system DC offset calibration.
12 I²S/LJ input Selects the serial audio interface format, either left-justified or I²S.
13 M0 input Mode select bit 0 which, together with M1, sets the speed mode (00 single-speed, 01 double-speed, 10 quad-speed, 11 reserved).
14 M1 input Mode select bit 1 which, together with M0, sets the speed mode (00 single-speed, 01 double-speed, 10 quad-speed, 11 reserved).
15 OVFL output Open-drain, active-low overflow output for both channels, requiring a 10 kΩ pull-up to VL when used and rated for a 4.0 mA maximum current sink.
16 AINL+ input Positive side of the differential left channel analog input to the delta-sigma modulator; full-scale input is 1.13VA typical (1.07VA to 1.18*VA) Vpp differential.
17 AINL- input Negative side of the differential left channel analog input to the delta-sigma modulator; full-scale input is 1.13VA typical (1.07VA to 1.18*VA) Vpp differential.
18 GND power_in Ground reference; must be connected to analog ground.
19 VA power_in Positive analog power supply for the analog section, specified 4.75 V to 5.25 V (5.0 V typical).
20 AINR- input Negative side of the differential right channel analog input to the delta-sigma modulator; full-scale input is 1.13VA typical (1.07VA to 1.18*VA) Vpp differential.
21 AINR+ input Positive side of the differential right channel analog input to the delta-sigma modulator; full-scale input is 1.13VA typical (1.07VA to 1.18*VA) Vpp differential.
22 VQ power_out Filter connection for the internal quiescent reference voltage, nominally 2.5 V with 25 kΩ output impedance and decoupling capacitors per the typical connection diagram.
23 REF_GND power_in Reference ground for the internal sampling circuits; FILT+ and VQ decoupling capacitors should be placed to minimize the path from FILT+ to REFGND.
24 FILT+ power_out Positive voltage reference output for the internal sampling circuits, nominally 5 V with 4.5 kΩ output impedance, and requires external decoupling capacitance that sets low-frequency distortion.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package TSSOP-24
Category Communication Interface Chip/UART/485/232
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Power Supplies: Analog VA 4.75 5 5.25 V GND = 0 V 5
DC Power Supplies: Positive Digital VD 3.1 5.25 V GND = 0 V 5
DC Power Supplies: Positive Logic VL 2.37 5.25 V GND = 0 V 5
Ambient Operating Temperature (Power Applied) TA -10 70 °C 5
DC Power Supplies: Analog VA -0.3 6 V All voltages with respect to ground 5
DC Power Supplies: Logic VL -0.3 6 V All voltages with respect to ground 5
DC Power Supplies: Digital VD -0.3 6 V All voltages with respect to ground 5
Digital Input Voltage (Note 3) VIND -0.7 V Max printed as VL+0.7 5
Ambient Operating Temperature (Power Applied) TA -50 95 °C 5
Storage Temperature Tstg -65 150 °C 5
Dynamic Range A-weighted 114 120 dB Single-Speed Mode Fs = 48 kHz 6
Dynamic Range unweighted 111 117 dB Single-Speed Mode Fs = 48 kHz 6
Gain Error -5 5 % 6
Gain Drift -100 100 ppm/°C 6
Passband (-0.1 dB) 0 0.47 Fs Single-Speed Mode (2 kHz to 54 kHz sample rates) 7
Passband Ripple -0.1 0.035 dB Single-Speed Mode (2 kHz to 54 kHz sample rates) 7
Stopband 0.58 Fs Single-Speed Mode (2 kHz to 54 kHz sample rates) 7
Stopband Attenuation -95 dB Single-Speed Mode (2 kHz to 54 kHz sample rates) 7
Passband (-0.1 dB) 0 0.45 Fs Double-Speed Mode (50 kHz to 108 kHz sample rates) 7
Stopband 0.68 Fs Double-Speed Mode (50 kHz to 108 kHz sample rates) 7
Stopband Attenuation -92 dB Double-Speed Mode (50 kHz to 108 kHz sample rates) 7
Passband (-0.1 dB) 0 0.24 Fs Quad-Speed Mode (100 kHz to 216 kHz sample rates) 7
Stopband 0.78 Fs Quad-Speed Mode (100 kHz to 216 kHz sample rates) 7
Stopband Attenuation -97 dB Quad-Speed Mode (100 kHz to 216 kHz sample rates) 7
Output Sample Rate Fs 2 54 kHz Single-Speed Mode 10
Output Sample Rate Fs 50 108 kHz Double-Speed Mode 10
Output Sample Rate Fs 100 216 kHz Quad-Speed Mode 10
MCLK Period tclkw 36 1953 ns 10
MCLK Duty Cycle 40 60 % 10
SCLK falling to LRCK transition tmslr -20 20 ns Master Mode 10
SCLK falling to SDOUT valid tsdo 32 ns Master Mode 10
SCLK Period tsclkw 145 ns Slave Mode, Single-Speed 10
SCLK Period tsclkw 72 ns Slave Mode, Quad-Speed 10
SDOUT valid before SCLK rising tstp 10 ns Slave Mode, Single-Speed 10
SDOUT valid after SCLK rising thld 5 ns Slave Mode, Single-Speed 10
SCLK falling to LRCK transition tslrd -8 8 ns Slave Mode, Quad-Speed 10
Power Supply Current (Normal Operation) IA 36 43 mA VA = 5 V 13
Power Supply Current (Normal Operation) ID 36 46 mA VL,VD = 5 V 13
Power Supply Current (Normal Operation) ID 24 28 mA VL,VD = 3.3 V 13
Power Consumption (Normal Operation) 360 445 mW VA, VL, VD = 5 V 13
Power Consumption (Normal Operation) 260 307 mW VA = 5 V; VL, VD = 3.3 V 13
High-Level Input Voltage (% of VL) VIH 70 % of VL 13
Low-Level Input Voltage (% of VL) VIL 30 % of VL 13
High-Level Output Voltage (% of VL) VOH 70 % of VL Io = 100 µA 13
Low-Level Output Voltage (% of VL) VOL 15 % of VL Io = 100 µA 13
OVFL Current Sink Iovfl 4 mA 13
Allowable Junction Temperature 135 °C 13
Junction to Ambient Thermal Impedance θJA-TM 70 °C/W Multi-layer PCB, TSSOP 13
Junction to Ambient Thermal Impedance θJA-TS 105 °C/W Single-layer PCB, TSSOP 13

CAD (KiCad official)

  • Symbol: CS5381-KZZR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cs5381-kzzr-etched.step / cs5381-kzzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs5381-kzzr.step / cs5381-kzzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (24 pp, sha256 7089630fbb53a7c1, retrieved 2026-11-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF