component
CS4354-CSZR
Public Made by Adomby adom
Cirrus Logic ADC/DAC - Specialized, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Ray
Publish 0.1.0
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{
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"version": "0.1.0",
"type": "component",
"description": "Cirrus Logic ADC/DAC - Specialized, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
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"adc-dac-data conversion",
"cs4354-cszr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"path": "docs/hero.png"
},
"files": [
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"cs4354-cszr.kicad_mod",
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"cs4354-cszr.step",
"cs4354-cszr.lbr",
"docs/hero.png",
"docs/cs4354-cszr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cs4354-cszr-hero.glb",
"cs4354-cszr-hero.overlay.json",
"cs4354-cszr-etched.glb"
],
"component": {
"mpn": "CS4354-CSZR",
"manufacturer": "Cirrus Logic",
"package": "SOIC-14",
"pin_count": 14,
"category": "ADC/DAC/Data Conversion",
"subcategory": "ADC/DAC - Specialized",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/bb84fccac2219962ad92db4c6162f3b0.pdf",
"parts": {
"symbol": "cs4354-cszr.kicad_sym",
"footprint": "cs4354-cszr.kicad_mod",
"model_3d": "cs4354-cszr-hero.glb",
"model_3d_plain": "cs4354-cszr-etched.glb",
"model_3d_step": "cs4354-cszr-etched.step",
"model_3d_step_plain": "cs4354-cszr.step",
"lbr": "cs4354-cszr.lbr"
},
"distributor_links": {
"lcsc": "C17564841",
"digikey": "CS4354-CSZR-ND",
"mouser": "777-CS4354CSZR"
},
"distributor_check": {
"checked_at": "2026-11-12T06:54:58Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "CS4354-CSZR-ND",
"status": "found"
},
"mouser": {
"pn": "777-CS4354CSZR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VL",
"type": "power_in",
"description": "Serial audio interface power input, specified from 1.4 V minimum to 5.25 V maximum with 1.8, 3.3 or 5.0 V typical, and logic levels must not exceed VL."
},
{
"number": "2",
"name": "SDIN",
"type": "input",
"description": "Two's complement serial audio data input, with digital input levels referenced to VL (1.8 V to 5 V receiver)."
},
{
"number": "3",
"name": "MCLK",
"type": "input",
"description": "Master clock input that clocks the delta-sigma modulator and digital filters, with digital input levels referenced to VL (1.8 V to 5 V receiver)."
},
{
"number": "4",
"name": "LRCK",
"type": "input",
"description": "Left/right clock input that selects which channel is active on the serial audio data line, with digital input levels referenced to VL (1.8 V to 5 V receiver)."
},
{
"number": "5",
"name": "SCLK/DEM",
"type": "input",
"description": "Serial clock input for the serial audio interface, with digital input levels referenced to VL (1.8 V to 5 V receiver)."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device; see Section 4.10 for layout considerations."
},
{
"number": "7",
"name": "FILT+",
"type": "power_out",
"description": "Positive reference voltage output for the internal sampling circuits, with its DC voltage to GND given in the DC output voltages table."
},
{
"number": "8",
"name": "AOUTA",
"type": "output",
"description": "Analog line output for the left channel, ground-centered with a 2 VRMS full-scale level as stated in the features and analog characteristics."
},
{
"number": "9",
"name": "AOUTB",
"type": "output",
"description": "Analog line output for the right channel, ground-centered with a 2 VRMS full-scale level as stated in the features and analog characteristics."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device; see Section 4.10 for layout considerations."
},
{
"number": "11",
"name": "VA",
"type": "power_in",
"description": "Analog, charge pump and regulator supply, specified from 4.75 V minimum to 5.25 V maximum with 5.0 V typical."
},
{
"number": "12",
"name": "FLYP",
"type": "output",
"description": "Positive node of the inverting charge pump flying capacitor, with its voltage to FLYN given in the DC output voltages table."
},
{
"number": "13",
"name": "FLYN",
"type": "output",
"description": "Negative node of the inverting charge pump flying capacitor, paired with FLYP."
},
{
"number": "14",
"name": "-VFILT",
"type": "power_out",
"description": "Negative rail output from the inverting charge pump filter that supplies the output amplifiers, with its voltage to GND given in the DC output voltages table."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin 5 is printed as SCLK/DEM; the pin table names only serial clock, so the de-emphasis function on ; The datasheet pin table gives one shared description for AOUTA and AOUTB; the per-channel descriptio; The datasheet lists GND on both pins 6 and 10 in one row; both are reported as separate entries with"
],
"pages_sent": 9,
"cost_usd": 0.0035,
"at": "2026-11-12T06:54:51"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/bb84fccac2219962ad92db4c6162f3b0.pdf",
"pages": 24,
"sha256": "46e15a5fdf011576",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 14,
"described": 14,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cs4354-cszr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
8.7,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cs4354-cszr-etched.step",
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"units": "mm",
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"seat": "z = 0",
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"footprint_binding": "identity",
"sha256": "1ebea3beb1746e7cacff71dc3dda214fa4288eba4dc3f98208218be552eb294b",
"checked": "2026-11-12",
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],
"package_dims": {
"package_code": "14L SOIC (150 MIL BODY)",
"source_page": 23,
"D": {
"nom_mm": 8.662,
"range_mm": [
8.585,
8.738
]
},
"E1": {
"nom_mm": 3.929,
"range_mm": [
3.861,
3.998
]
},
"E": {
"nom_mm": 6.02,
"range_mm": [
5.842,
6.198
]
},
"e": {
"nom_mm": 1.27,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.626,
"range_mm": [
1.524,
1.727
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "cs4354-cszr.step",
"verdict": "PASS",
"reasons": [
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],
"by": "factory/package_fit.py"
}
}
}
}