component

CS4354-CSZR

Public Made by Adom

by adom

Cirrus Logic ADC/DAC - Specialized, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversioncs4354-cszrfactory-2.0.0extractor-text

Verified CS4354-CSZR

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier lcsc, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS4354-CSZR · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C17564841, digikey CS4354-CSZR-ND, mouser 777-CS4354CSZR
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1iqq8ix2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.23)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 31 kB, viewers/symbol.html 13 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs4354-cszr.kicad_sym✓ cs4354-cszr.kicad_mod✓ cs4354-cszr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cs4354-cszr: viewers rendered from the public page · Ray
cs4354-cszr-etched.glb Publish 0.1.0 · Ray
cs4354-cszr-etched.step cs4354-cszr: factory component page (tier=lcsc) · Ray
cs4354-cszr-hero.glb cs4354-cszr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs4354-cszr-hero.overlay.json cs4354-cszr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs4354-cszr.glb Publish 0.1.0 · Ray
cs4354-cszr.kicad_mod Publish 0.1.0 · Ray
cs4354-cszr.kicad_sym Publish 0.1.0 · Ray
cs4354-cszr.lbr Publish 0.1.0 · Ray
cs4354-cszr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 14 pins · Ray

CS4354-CSZR

Cirrus Logic · ADC/DAC - Specialized · SOIC-14

CS4354-CSZR from Cirrus Logic, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VL power_in Serial audio interface power input, specified from 1.4 V minimum to 5.25 V maximum with 1.8, 3.3 or 5.0 V typical, and logic levels must not exceed VL.
2 SDIN input Two's complement serial audio data input, with digital input levels referenced to VL (1.8 V to 5 V receiver).
3 MCLK input Master clock input that clocks the delta-sigma modulator and digital filters, with digital input levels referenced to VL (1.8 V to 5 V receiver).
4 LRCK input Left/right clock input that selects which channel is active on the serial audio data line, with digital input levels referenced to VL (1.8 V to 5 V receiver).
5 SCLK/DEM input Serial clock input for the serial audio interface, with digital input levels referenced to VL (1.8 V to 5 V receiver).
6 GND power_in Ground reference for the device; see Section 4.10 for layout considerations.
7 FILT+ power_out Positive reference voltage output for the internal sampling circuits, with its DC voltage to GND given in the DC output voltages table.
8 AOUTA output Analog line output for the left channel, ground-centered with a 2 VRMS full-scale level as stated in the features and analog characteristics.
9 AOUTB output Analog line output for the right channel, ground-centered with a 2 VRMS full-scale level as stated in the features and analog characteristics.
10 GND power_in Ground reference for the device; see Section 4.10 for layout considerations.
11 VA power_in Analog, charge pump and regulator supply, specified from 4.75 V minimum to 5.25 V maximum with 5.0 V typical.
12 FLYP output Positive node of the inverting charge pump flying capacitor, with its voltage to FLYN given in the DC output voltages table.
13 FLYN output Negative node of the inverting charge pump flying capacitor, paired with FLYP.
14 -VFILT power_out Negative rail output from the inverting charge pump filter that supplies the output amplifiers, with its voltage to GND given in the DC output voltages table.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package SOIC-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC power supply, analog power VA 4.75 5 5.25 V 5
DC power supply, interface power VL 1.4 5.25 V 5
Ambient operating temperature (power applied), -CSZ TA -40 85 °C Power applied 5
DC power supply, low voltage analog power VA -0.3 6 V 5
DC power supply, interface power VL -0.3 6 V 5
Input current, any pin except supplies Iin -10 10 mA 5
Digital input voltage, digital interface VIN-L -0.3 V Note 2 (maximum given as VL + 0.4 V) 5
Ambient operating temperature (power applied) TA -55 125 °C Power applied 5
Storage temperature Tstg -65 150 °C 5
Dynamic range 24-bit A-weighted 95 101 dB Fs = 48, 96, and 192 kHz; TA = 25 °C; VA = 5 V, VL = 3.3 V 6
Dynamic range 24-bit unweighted 92 98 dB Fs = 48, 96, and 192 kHz; TA = 25 °C; VA = 5 V, VL = 3.3 V 6
Output offset -8 1 8 mV TA = 25 °C; VA = 5 V, VL = 3.3 V 6
Load resistance RL 3 kΩ TA = 25 °C; VA = 5 V, VL = 3.3 V 6
Load capacitance CL 100 pF TA = 25 °C; VA = 5 V, VL = 3.3 V 6
Single-Speed 48 kHz frequency response -0.05 0.05 dB 20 Hz to 20 kHz 7
Single-Speed 48 kHz stopband 0.55 Fs Single-Speed Mode 48 kHz 7
Single-Speed 48 kHz stopband attenuation 80 dB Single-Speed Mode 48 kHz (Note 9) 7
De-emphasis error (relative to 1 kHz) -0.14 0.14 dB Fs = 44.1 kHz (Note 10) 7
Double-Speed 96 kHz frequency response -0.05 0.05 dB 20 Hz to 20 kHz 7
Double-Speed 96 kHz stopband 0.583 Fs Double-Speed Mode 96 kHz 7
Double-Speed 96 kHz stopband attenuation 82 dB Double-Speed Mode 96 kHz (Note 9) 7
Quad-Speed 192 kHz frequency response -0.05 0.05 dB 20 Hz to 20 kHz 7
Quad-Speed 192 kHz stopband 0.63 Fs Quad-Speed Mode 192 kHz 7
Quad-Speed 192 kHz stopband attenuation 85 dB Quad-Speed Mode 192 kHz (Note 9) 7
MCLK frequency 7.6 55.3 MHz 8
MCLK duty cycle 35 65 % 8
Input sample rate, all MCLK/LRCK ratios combined Fs 30 216 kHz All MCLK/LRCK ratios combined (Note 12) 8
Input sample rate, Single-Speed Mode Fs 30 54 kHz (SSM) 256x, 384x, 512x, 768x, 1024x 8
Input sample rate, Double-Speed Mode Fs 84 108 kHz (DSM) 128x, 192x, 256x, 384x, 512x 8
Input sample rate, Quad-Speed Mode Fs 170 216 kHz (QSM) 128x, 192x, 256x 8
External SCLK mode LRCK duty cycle 45 55 % External SCLK Mode 8
SCLK pulse width low tsclkl 20 ns External SCLK Mode 8
SCLK pulse width high tsclkh 20 ns External SCLK Mode 8
SCLK duty cycle 45 55 % External SCLK Mode 8
SCLK rising to LRCK edge delay tslrd 20 ns External SCLK Mode 8
LRCK edge to SCLK rising delay tslrs 20 ns External SCLK Mode 8
SDIN valid to SCLK rising setup time tsdlrs 20 ns External SCLK Mode 8
SCLK rising to SDIN hold time tsdh 20 ns External SCLK Mode 8
Input leakage current Iin -10 10 µA Digital interface inputs 10
Power supply current, IVA, normal operation IVA 10 13 mA Normal operation (Note 16) 11
Power supply current, IVL, normal operation IVL 0.1 0.2 mA Normal operation (Note 16) 11
Power dissipation, all supplies, normal operation 50 65 mW Normal Operation (Note 16) 11
Junction-to-ambient thermal impedance, 2-layer board JA 110 °C/Watt 2-layer board 23
Junction-to-ambient thermal impedance, 4-layer board JA 86 °C/Watt 4-layer board 23

CAD (KiCad official)

  • Symbol: CS4354-CSZR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cs4354-cszr-etched.step / cs4354-cszr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs4354-cszr.step / cs4354-cszr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (24 pp, sha256 46e15a5fdf011576, retrieved 2026-11-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF