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CS32F103RBT7

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CHIPSEA Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS32F103RBT7

CHIPSEA · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

CS32F103RBT7 from CHIPSEA, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Supplies the I/O pins and internal voltage regulator, 2.0 to 3.6 V.
2 PC13/TAMPER_RTC bidirectional Powered through a switch limited to 3 mA; as output only one of PC13-PC15 may drive at a time, at 2 MHz max with 30 pF load, and it cannot source current such as an LED.
3 PC14/OSC32_IN bidirectional Powered through the same 3 mA-limited switch as PC13; serves as the 32.768 kHz LSE oscillator input OSC32_IN.
4 PC15/OSC32_OUT bidirectional Powered through the same 3 mA-limited switch as PC13; serves as the 32.768 kHz LSE oscillator output OSC32_OUT.
5 PD0/OSC_IN input Defaults to HXT oscillator input OSC_IN after reset and can be reassigned to PD0 in software.
6 PD1/OSC_OUT output Defaults to HXT oscillator output OSC_OUT after reset and can be reassigned to PD1 in software; in output mode it is limited to 50 MHz.
7 NRST input Active-low reset input with an internal pull-up of about 80 kΩ; VIL max 0.8 V and VIH min 2 V.
8 PC0 bidirectional General-purpose I/O with ADC12_IN10 analog input.
9 PC1 bidirectional General-purpose I/O with ADC12_IN11 analog input.
10 PC2 bidirectional General-purpose I/O with ADC12_IN12 analog input.
11 PC3 bidirectional General-purpose I/O with ADC12_IN13 analog input.
12 VSSA power_in Analog ground for the ADC, reset block, RC oscillators and PLL; must be connected to VSS.
13 VDDA power_in Analog supply for the ADC, reset block, RC oscillators and PLL, 2.0 to 3.6 V; must be at least 2.4 V when the ADC is used.
14 PA0-WKUP bidirectional General-purpose I/O that also serves as WKUP wake-up input (rising edge) with USART2_CTS, ADC12_IN0 and TIM2 channel 1/ETR.
15 PA1 bidirectional General-purpose I/O with USART2_RTS, ADC12_IN1 and TIM2_CH2.
16 PA2 bidirectional General-purpose I/O with USART2_TX, ADC12_IN2 and TIM2_CH3.
17 PA3 bidirectional General-purpose I/O with USART2_RX, ADC12_IN3 and TIM2_CH4.
18 VSS power_in Ground reference for the digital core and I/O pins.
19 VDD power_in Supplies the I/O pins and internal voltage regulator, 2.0 to 3.6 V.
20 PA4 bidirectional General-purpose I/O with SPI1_NSS, USART2_CK and ADC12_IN4.
21 PA5 bidirectional General-purpose I/O with SPI1_SCK and ADC12_IN5.
22 PA6 bidirectional General-purpose I/O with SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN.
23 PA7 bidirectional General-purpose I/O with SPI1_MOSI, ADC12_IN7, TIM3_CH2 and TIM1_CHIN.
24 PC4 bidirectional General-purpose I/O with ADC12_IN14 analog input.
25 PC5 bidirectional General-purpose I/O with ADC12_IN15 analog input.
26 PB0 bidirectional General-purpose I/O with ADC12_IN8, TIM3_CH3 and TIM1_CH2N.
27 PB1 bidirectional General-purpose I/O with ADC12_IN9, TIM3_CH4 and TIM1_CH3N.
28 PB2/BOOT1 bidirectional 5 V tolerant I/O (FT) that also serves as the BOOT1 boot-mode select input.
29 PB10 bidirectional 5 V tolerant I/O (FT) with I2C2_SCL, USART3_TX and TIM2_CH3.
30 PB11 bidirectional 5 V tolerant I/O (FT) with I2C2_SDA, USART3_RX and TIM2_CH4.
31 VSS power_in Ground reference for the digital core and I/O pins.
32 VDD power_in Supplies the I/O pins and internal voltage regulator, 2.0 to 3.6 V.
33 PB12 bidirectional 5 V tolerant I/O (FT) with SPI2_NSS, I2C2_SMBA, USART3_CK and TIM1_BKIN.
34 PB13 bidirectional 5 V tolerant I/O (FT) with SPI2_SCK, USART3_CTS and TIM1_CH1N.
35 PB14 bidirectional 5 V tolerant I/O (FT) with SPI2_MISO, USART3_RTS and TIM1_CH2N.
36 PB15 bidirectional 5 V tolerant I/O (FT) with SPI2_MOSI and TIM1_CH3N.
37 PC6 bidirectional 5 V tolerant I/O (FT) with TIM3_CH1.
38 PC7 bidirectional 5 V tolerant I/O (FT) with TIM3_CH2.
39 PC8 bidirectional 5 V tolerant I/O (FT) with TIM3_CH3.
40 PC9 bidirectional 5 V tolerant I/O (FT) with TIM3_CH4.
41 PA8 bidirectional 5 V tolerant I/O (FT) with USART1_CK, TIM1_CH1 and MCO.
42 PA9 bidirectional 5 V tolerant I/O (FT) with USART1_TX and TIM1_CH2.
43 PA10 bidirectional 5 V tolerant I/O (FT) with USART1_RX and TIM1_CH3.
44 PA11 bidirectional 5 V tolerant I/O (FT) with USART1_CTS, USBDM, CANRX and TIM1_CH4.
45 PA12 bidirectional 5 V tolerant I/O (FT) with USART1_RTS, USBDP, CANTX and TIM1_ETR.
46 PA13 bidirectional 5 V tolerant I/O (FT) that serves as the JTMS/SWDIO debug pin.
47 VSS power_in Ground reference for the digital core and I/O pins.
48 VDD power_in Supplies the I/O pins and internal voltage regulator, 2.0 to 3.6 V.
49 PA14 bidirectional 5 V tolerant I/O (FT) that serves as the JTCK/SWCLK debug clock pin.
50 PA15 bidirectional 5 V tolerant I/O (FT) that defaults to JTDI; SWJ must be disabled before it can be used as a general-purpose I/O.
51 PC10 bidirectional 5 V tolerant I/O (FT) with USART3_TX.
52 PC11 bidirectional 5 V tolerant I/O (FT) with USART3_RX.
53 PC12 bidirectional 5 V tolerant I/O (FT) with USART3_CK.
54 PD2 bidirectional 5 V tolerant I/O (FT) with TIM3_ETR.
55 PB3 bidirectional 5 V tolerant I/O (FT) that defaults to JTDO with TRACESWO, TIM2_CH2 and SPI1_SCK.
56 PB4 bidirectional 5 V tolerant I/O (FT) that defaults to NJTRST with TIM3_CH1 and SPI1_MISO.
57 PB5 bidirectional General-purpose I/O with I2C1_SMBA, TIM3_CH2 and SPI1_MOSI.
58 PB6 bidirectional 5 V tolerant I/O (FT) with I2C1_SCL, TIM4_CH1 and USART1_TX.
59 PB7 bidirectional 5 V tolerant I/O (FT) with I2C1_SDA, TIM4_CH2 and USART1_RX.
60 BOOT0 input Boot mode select input; the datasheet gives an input range of 0 to 5.5 V for BOOT0.
61 PB8 bidirectional 5 V tolerant I/O (FT) with TIM4_CH3, I2C1_SCL and CANRX.
62 PB9 bidirectional 5 V tolerant I/O (FT) with TIM4_CH4, I2C1_SDA and CANTX.
63 VSS power_in Ground reference for the digital core and I/O pins.
64 VDD power_in Supplies the I/O pins and internal voltage regulator, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
外部主供电电压(包含VDDA和VDD) VDD, VSS -0.3 4 V 24
在5V耐压的引脚上的输入电压 VIN -0.3 5.5 V 24
在其它引脚上的输入电压 VIN -0.3 4 V 24
不同供电引脚之间的电压差 /ΔVDDx/ 50 mV 24
不同接地引脚之间的电压差 /VSSX, VSS/ 50 mV 24
VDD工作电压(功能特点) VDD 2 3.6 V 1
VDDA工作电压(功能特点) VDDA 2 3.6 V 1
USB收发器启动时间 tSTARTUP 1 μs 44
USB操作电压 VDD 3 3.6 V 44
差分输入灵敏度 VDI 0.2 V I(USBDP,USBDM) 44
差分共模范围 VCM 0.8 2.5 V 包含VDI范围 44
单端接收器阀值 VSE 1.3 2 V 44
静态输出低电平 VOL 0.3 V 1.5kΩ 的RL接至 3.6V 44
静态输出高电平 VOH 2.8 3.6 V 15kΩ 的RL接至 VSS 44
上升时间 tr 4 20 ns CL ≤ 50pF 45
下降时间 tf 4 20 ns CL ≤ 50pF 45
上升下降时间匹配 trfm 90 110 % tr / tf 45
输出信号交叉电压 VCRS 1.3 2 V 45
供电电压 VDDA 2.4 3.6 V 45
ADC时钟频率 fADC 0.6 14 MHz 45
采样速率 fS 0.05 1 MHz 45
外部触发频率 fTRIG 823 kHz fADC=14MHz 45
在V输入脚上的电流 IVREF 160 220 μA 45
外部输入阻抗 RAIN 50 kΩ 45
采样开关电阻 RADC 1 kΩ 45
内部采样和保持电容 CADC 8 pF 45
上电时间 tSTAB 0 0 1 μs 46
总的转换时间(包括采样时间) tCONV 1 18 μs fADC=14MHz 46
采样时间 ts 0.107 17.1 μs fADC=14MHz 46
综合误差 ET 1.3 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
偏移误差 EO 1 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
增益误差 EG 0.5 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
微分线性误差 ED 0.7 1 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
积分线性误差 EL 1.5 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46

CAD (KiCad official)

  • Symbol: CS32F103RBT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: cs32f103rbt7-etched.step / cs32f103rbt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32f103rbt7.step / cs32f103rbt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (66 pp, sha256 d784567231c328d7, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF