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CS32F103CBT7

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CHIPSEA New Arrivals, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS32F103CBT7

CHIPSEA · New Arrivals · LQFP-48(7x7)

CS32F103CBT7 from CHIPSEA, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply for the I/O pins and internal voltage regulator, specified at 2.0 V to 3.6 V.
2 PC13 bidirectional GPIO PC13 with TAMPER-RTC function; it is powered through a power switch that sinks only 3 mA, so only one of PC13 to PC15 may be an output at a time, limited to 2 MHz with a 30 pF load, and it cannot be used as a current source such as an LED driver.
3 PC14 bidirectional GPIO PC14 that doubles as OSC32_IN for the 32.768 kHz low-speed oscillator, with the same 3 mA power-switch and output limits as PC13 to PC15.
4 PC15 bidirectional GPIO PC15 that doubles as OSC32_OUT for the 32.768 kHz low-speed oscillator, with the same 3 mA power-switch and output limits as PC13 to PC15.
5 OSC_IN input High-speed external oscillator input for a 4 to 16 MHz crystal or resonator; after reset this pin is OSC_IN and software can reconfigure it as PD0.
6 OSC_OUT output High-speed external oscillator output for a 4 to 16 MHz crystal or resonator; after reset this pin is OSC_OUT and software can reconfigure it as PD1.
7 NRST input Active-low reset input with an internal pull-up of about 80 kΩ; the datasheet gives VIL max 0.8 V and VIH min 2 V.
8 VSSA power_in Analog ground for the ADC, reset block, RC oscillators and PLL, which must be connected to VSS.
9 VDDA power_in Analog supply for the ADC, reset block, RC oscillators and PLL, specified at 2.0 V to 3.6 V and at least 2.4 V when the ADC is used, and must be connected to VDD.
10 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up function and alternates ADC12_IN0, USART2_CTS and TIM2_CH1_ETR (TIM2_TI1 or TIM2_ETR); it is not marked as 5 V tolerant.
11 PA1 bidirectional GPIO PA1 with alternates USART2_RTS, ADC12_IN1 and TIM2_CH2; it is not marked as 5 V tolerant.
12 PA2 bidirectional GPIO PA2 with alternates USART2_TX, ADC12_IN2 and TIM2_CH3; it is not marked as 5 V tolerant.
13 PA3 bidirectional GPIO PA3 with alternates USART2_RX, ADC12_IN3 and TIM2_CH4; it is not marked as 5 V tolerant.
14 PA4 bidirectional GPIO PA4 with alternates SPI1_NSS, USART2_CK and ADC12_IN4; it is not marked as 5 V tolerant.
15 PA5 bidirectional GPIO PA5 with alternates SPI1_SCK and ADC12_IN5; it is not marked as 5 V tolerant.
16 PA6 bidirectional GPIO PA6 with alternates SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN; it is not marked as 5 V tolerant.
17 PA7 bidirectional GPIO PA7 with alternates SPI1_MOSI, ADC12_IN7, TIM3_CH2 and TIM1_CHIN; it is not marked as 5 V tolerant.
18 PB0 bidirectional GPIO PB0 with alternates ADC12_IN8, TIM3_CH3 and TIM1_CH2N; it is not marked as 5 V tolerant.
19 PB1 bidirectional GPIO PB1 with alternates ADC12_IN9, TIM3_CH4 and TIM1_CH3N; it is not marked as 5 V tolerant.
20 PB2/BOOT1 bidirectional 5 V-tolerant GPIO PB2 that also serves as the BOOT1 boot-mode pin.
21 PB10 bidirectional 5 V-tolerant GPIO PB10 with alternates I2C2_SCL, USART3_TX and TIM2_CH3.
22 PB11 bidirectional 5 V-tolerant GPIO PB11 with alternates I2C2_SDA, USART3_RX and TIM2_CH4.
23 VSS power_in Ground reference; all VSS pins must be connected to the external supply within the permitted range, and the difference between ground pins must not exceed 50 mV.
24 VDD power_in Power supply for the I/O pins and internal voltage regulator, specified at 2.0 V to 3.6 V.
25 PB12 bidirectional 5 V-tolerant GPIO PB12 with alternates SPI2_NSS, I2C2_SMBA, USART3_CK and TIM1_BKIN.
26 PB13 bidirectional 5 V-tolerant GPIO PB13 with alternates SPI2_SCK, USART3_CTS and TIM1_CH1N.
27 PB14 bidirectional 5 V-tolerant GPIO PB14 with alternates SPI2_MISO, USART3_RTS and TIM1_CH2N.
28 PB15 bidirectional 5 V-tolerant GPIO PB15 with alternates SPI2_MOSI and TIM1_CH3N.
29 PA8 bidirectional 5 V-tolerant GPIO PA8 with alternates USART1_CK, TIM1_CH1 and MCO.
30 PA9 bidirectional 5 V-tolerant GPIO PA9 with alternates USART1_TX and TIM1_CH2.
31 PA10 bidirectional 5 V-tolerant GPIO PA10 with alternates USART1_RX and TIM1_CH3.
32 PA11 bidirectional 5 V-tolerant GPIO PA11 with alternates USART1_CTS, USBDM, CANRX and TIM1_CH4.
33 PA12 bidirectional 5 V-tolerant GPIO PA12 with alternates USART1_RTS, USBDP, CANTX and TIM1_ETR.
34 PA13 bidirectional 5 V-tolerant pin with JTMS/SWDIO serial-wire debug function (SWJ-DP), usable as GPIO PA13 when SWJ is not used.
35 VSS power_in Ground reference; all VSS pins must be connected to the external supply within the permitted range, and the difference between ground pins must not exceed 50 mV.
36 VDD power_in Power supply for the I/O pins and internal voltage regulator, specified at 2.0 V to 3.6 V.
37 PA14 bidirectional 5 V-tolerant pin with JTCK/SWCLK serial-wire debug function, usable as GPIO PA14 when SWJ is not used.
38 PA15 bidirectional 5 V-tolerant pin that defaults to the JTDI JTAG function with alternates TIM2_CH1_ETR and SPI1_NSS; SWJ must be disabled before it can be used as a normal GPIO.
39 PB3 bidirectional 5 V-tolerant pin with JTDO/TRACESWO function and alternates TIM2_CH2 and SPI1_SCK, usable as GPIO PB3 when not used for debug.
40 PB4 bidirectional 5 V-tolerant pin with NJTRST function and alternates TIM3_CH1 and SPI1_MISO, usable as GPIO PB4 when not used for debug.
41 PB5 bidirectional GPIO PB5 with alternates I2C1_SMBA, TIM3_CH2 and SPI1_MOSI; it is not marked as 5 V tolerant.
42 PB6 bidirectional 5 V-tolerant GPIO PB6 with alternates I2C1_SCL, TIM4_CH1 and USART1_TX.
43 PB7 bidirectional 5 V-tolerant GPIO PB7 with alternates I2C1_SDA, TIM4_CH2 and USART1_RX.
44 BOOT0 input Boot mode selection pin, specified from 0 to 5.5 V and used with BOOT1 to select boot from main Flash, system memory or internal SRAM at startup.
45 PB8 bidirectional 5 V-tolerant GPIO PB8 with alternates TIM4_CH3, I2C1_SCL and CANRX.
46 PB9 bidirectional 5 V-tolerant GPIO PB9 with alternates TIM4_CH4, I2C1_SDA and CANTX.
47 VSS power_in Ground reference; all VSS pins must be connected to the external supply within the permitted range, and the difference between ground pins must not exceed 50 mV.
48 VDD power_in Power supply for the I/O pins and internal voltage regulator, specified at 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package LQFP-48(7x7)
Category Others
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
外部主供电电压(包含VDDA和VDD) VDD, VSS -0.3 4 V 24
在5V耐压的引脚上的输入电压 VIN 5.5 V 24
在其它引脚上的输入电压 VIN 4 V 24
不同供电引脚之间的电压差 /ΔVDDx/ 50 mV 24
不同接地引脚之间的电压差 /VSSX, VSS/ 50 mV 24
VDD 电压(产品特性概述) VDD 2 3.6 V 1
VDDA 电压(产品特性概述) VDDA 2 3.6 V 1
环境温度 -40 85 ℃ 页面印刷为 -40~85/105℃, 105 档未按后缀解码 1
USB 收发器启动时间 tSTARTUP 1 μs 44
USB操作电压 VDD 3 3.6 V 44
差分输入灵敏度 VDI 0.2 V I(USBDP,USBDM) 44
差分共模范围 0.8 2.5 V 包含VDI范围 44
单端接收器阀值 VSE 1.3 2 V 44
静态输出低电平 VOL 0.3 V 1.5kΩ 的RL接至 3.6V 44
静态输出高电平 VOH 2.8 3.6 V 15kΩ 的RL接至 VSS 44
上升时间 tr 4 20 ns CL ≤ 50pF 45
下降时间 tf 4 20 ns CL ≤ 50pF 45
上升下降时间匹配 tr/tf trfm 90 110 % 45
输出信号交叉电压 VCRS 1.3 2 V 45
ADC 供电电压 VDDA 2.4 3.6 V 45
正参考电压 VREF+ 2.4 V 45
在 V 输入脚上的电流 IVREF 160 220 μA 45
ADC时钟频率 fADC 0.6 14 MHz 45
采样速率 fS 0.05 1 MHz 45
外部触发频率 fTRIG 823 kHz fADC=14MHz 45
外部触发频率 fTRIG 17 1/fADC 45
转换电压范围 VAIN 0 V VSSA 或 VREF- 连接到地 45
外部输入阻抗 RAIN 50 kΩ 45
采样开关电阻 RADC 1 kΩ 45
内部采样和保持电容 CADC 8 pF 45
注入触发转换时延 tlat 0.214 μs fADC=14MHz 46
注入触发转换时延 tlat 3 1/fADC 46
常规触发转换时延 tlatr 0.143 μs fADC=14MHz 46
常规触发转换时延 tlatr 2 1/fADC 46
采样时间 ts 0.107 17.1 μs fADC=14MHz 46
采样时间 ts 1.5 239.5 1/fADC 46
上电时间 tSTAB 0 0 1 μs 46
总的转换时间(包括采样时间) tCONV 1 18 μs fADC=14MHz 46
总的转换时间(包括采样时间) tCONV 14 252 1/fADC 采样 tS+逐步逼近 12.5 46
最大 RAIN (TS=1.5 周期, tS=0.11 μs) RAIN 0.4 kΩ fADC=14MHz 46
最大 RAIN (TS=7.5 周期, tS=0.54 μs) RAIN 5.9 kΩ fADC=14MHz 46
最大 RAIN (TS=13.5 周期, tS=0.96 μs) RAIN 11.4 kΩ fADC=14MHz 46
最大 RAIN (TS=28.5 周期, tS=2.04 μs) RAIN 25.2 kΩ fADC=14MHz 46
最大 RAIN (TS=41.5 周期, tS=2.96 μs) RAIN 37.2 kΩ fADC=14MHz 46
最大 RAIN (TS=55.5 周期, tS=3.96 μs) RAIN 50 kΩ fADC=14MHz 46
综合误差 ET -2 1.3 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C; 测量是在 ADC 校准之后进行的 46
偏移误差 EO -1.5 1 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C; 测量是在 ADC 校准之后进行的 46
增益误差 EG -1.5 0.5 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C; 测量是在 ADC 校准之后进行的 46
微分线性误差 ED -1 0.7 1 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C; 测量是在 ADC 校准之后进行的 46
积分线性误差 EL -2 1.5 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C; 测量是在 ADC 校准之后进行的 46

CAD (KiCad official)

  • Symbol: CS32F103CBT7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cs32f103cbt7-etched.step / cs32f103cbt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32f103cbt7.step / cs32f103cbt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (66 pp, sha256 c63c9196e83fb8cd, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF