component

CS2300CP-CZZR

Public Made by Adom

by adom

Cirrus Logic Clock Generators, PLLs, Frequency Synthesizers, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cs2300cp-czzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cs2300cp-czzr: viewers · Ray
cs2300cp-czzr-etched.fit.json cs2300cp-czzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cs2300cp-czzr-etched.glb cs2300cp-czzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cs2300cp-czzr-etched.step cs2300cp-czzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cs2300cp-czzr.glb Publish 0.1.0 · Ray
cs2300cp-czzr.kicad_mod Publish 0.1.0 · Ray
cs2300cp-czzr.kicad_sym Publish 0.1.0 · Ray
cs2300cp-czzr.lbr Publish 0.1.0 · Ray
cs2300cp-czzr.step Publish 0.1.0 · Ray
package.json cs2300cp-czzr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cs2300cp-czzr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cs2300cp-czzr · Ray

CS2300CP-CZZR

Cirrus Logic · Clock Generators, PLLs, Frequency Synthesizers · MSOP-10

CS2300CP-CZZR from Cirrus Logic, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VD power_in Digital power supply input (3.1-3.5 V) for digital and analog sections.
2 GND power_in Ground reference.
3 CLK_OUT output PLL clock output providing low-jitter clock at 6-75 MHz.
4 AUX_OUT output Auxiliary output selectable as buffered CLK_IN, CLK_OUT, or lock indicator via register configuration.
5 CLK_IN input Frequency reference clock input (50 Hz-30 MHz) for Digital PLL.
6 FILTP bidirectional LC oscillator filter positive pin; connect 0.1 µF capacitor to FILTN for external supply filtering.
7 FILTN bidirectional LC oscillator filter negative pin; connect 0.1 µF capacitor to FILTP and tie to GND.
8 AD0/CS input Address/chip select input; I²C mode via permanent connection to VD or GND, SPI mode via high-to-low transition after power-up.
9 SCL/CCLK input Serial clock input; 100 kHz maximum (I²C) or 6 MHz maximum (SPI).
10 SDA/CDIN bidirectional Serial data line; bidirectional in I²C mode (SDA) or input-only in SPI mode (CDIN) with open-drain driver.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package MSOP-10
Category Clock/Timing
Pins 10

CAD (KiCad official)

  • Symbol: CS2300CP-CZZR
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: cs2300cp-czzr-etched.step / cs2300cp-czzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs2300cp-czzr.step / cs2300cp-czzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (32 pp, sha256 2938c833dd2affd8, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF