component
CS2000CP-CZZR
Public Made by Adomby adom
Cirrus Logic Clock Generators / Frequency Synthesizers / PLL, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Set visibility: public
77d28ee
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010
{
"schema_version": 1,
"type": "component",
"slug": "cs2000cp-czzr",
"title": "CS2000CP-CZZR",
"brief": "Cirrus Logic Clock Generators / Frequency Synthesizers / PLL, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"rtc-clock chip",
"cs2000cp-czzr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "CS2000CP-CZZR",
"manufacturer": "Cirrus Logic",
"package": "MSOP-10",
"pin_count": 10,
"category": "RTC/Clock Chip",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/e1813d77b335aa67eea6072c0689eeb4.pdf",
"parts": {
"symbol": "cs2000cp-czzr.kicad_sym",
"footprint": "cs2000cp-czzr.kicad_mod",
"model_3d": "cs2000cp-czzr-hero.glb",
"model_3d_plain": "cs2000cp-czzr-etched.glb",
"model_3d_step": "cs2000cp-czzr-etched.step",
"model_3d_step_plain": "cs2000cp-czzr.step",
"lbr": "cs2000cp-czzr.lbr"
},
"distributor_links": {
"lcsc": "C1536642",
"digikey": "598-1399-2-ND"
},
"distributor_check": {
"checked_at": "2026-11-05T17:13:11Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "598-1399-2-ND",
"status": "found",
"lifecycle": "Obsolete"
},
"mouser": {
"pn": null,
"status": "error"
}
},
"pins": [
{
"number": "1",
"name": "VD",
"type": "power_in",
"description": "Positive power supply for the digital and analog sections of the device."
},
{
"number": "2",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device."
},
{
"number": "3",
"name": "CLK_OUT",
"type": "output",
"description": "PLL clock output, the output of the PLL clock path."
},
{
"number": "4",
"name": "AUX_OUT",
"type": "output",
"description": "Buffered version of one of the input or output clocks, or a status signal, selected by register configuration."
},
{
"number": "5",
"name": "CLK_IN",
"type": "input",
"description": "Clock input for the Digital PLL frequency reference."
},
{
"number": "6",
"name": "XTO",
"type": "bidirectional",
"description": "Crystal connection pin used with XTI for an external crystal that generates the low-jitter PLL input clock."
},
{
"number": "7",
"name": "XTI/REF_CLK",
"type": "bidirectional",
"description": "Crystal connection XTI (I/O for an external crystal) or timing reference clock input REF_CLK for an externally generated low-jitter reference clock."
},
{
"number": "8",
"name": "AD0/CS",
"type": "input",
"description": "Address bit 0 (chip address pin) in I²C mode, and control port chip select signal in SPI mode."
},
{
"number": "9",
"name": "SCL/CCLK",
"type": "input",
"description": "Serial clock for the serial control port in I²C and SPI mode."
},
{
"number": "10",
"name": "SDA/CDIN",
"type": "bidirectional",
"description": "Serial data I/O line in I²C mode, and input data line for the control port interface in SPI mode."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet pin table gives the crystal/REF_CLK pins only as 'Input/Output' without a KiCad class;; Pin table gives no voltage limits for VD; the Recommended Operating Conditions and DC characteristic"
],
"pages_sent": 9,
"cost_usd": 0.044,
"at": "2026-11-05T17:12:59"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/e1813d77b335aa67eea6072c0689eeb4.pdf",
"pages": 37,
"sha256": "c5a9b4f7822cfff6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 10,
"described": 10,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cs2000cp-czzr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.9,
3,
1.1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "b8f88eac3ce221c2ccb0b5048f9ad49c2ef4af148f8ae50c4e232e357683f547",
"checked": "2026-11-05",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cs2000cp-czzr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.9,
3,
1.1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "b1666a6bd53a4e8753cbc9af5f41e4fda8c42ee2bbb1ceca940e24cf552f9179",
"checked": "2026-11-05",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "10L MSOP (3 mm BODY)",
"source_page": 35,
"D": {
"nom_mm": 3,
"range_mm": [
null,
null
]
},
"E1": {
"nom_mm": 3,
"range_mm": [
null,
null
]
},
"E": {
"nom_mm": 4.9,
"range_mm": [
null,
null
]
},
"e": {
"nom_mm": 0.5,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.1,
"range_mm": [
null,
1.1
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "cs2000cp-czzr.step",
"verdict": "PASS",
"reasons": [
"height and body within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
},
"metadata": {
"specs": {
"Manufacturer": "Cirrus Logic",
"Package": "MSOP-10",
"Category": "RTC/Clock Chip",
"Pins": "10"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "c5a9b4f7822cfff63579336a41f0e068a24ed53dd251dad63072fe00cce706a3",
"rows": [
{
"name": "DC Power Supply",
"symbol": "VD",
"kind": "recommended_operating",
"unit": "V",
"min": 3.1,
"typ": 3.3,
"max": 3.5,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Ambient Operating Temperature (Power Applied) Commercial Grade",
"symbol": "TAC",
"kind": "recommended_operating",
"unit": "°C",
"min": -10,
"typ": null,
"max": 70,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "DC Power Supply",
"symbol": "VD",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": 6,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Input Current",
"symbol": "IIN",
"kind": "absolute_maximum",
"unit": "mA",
"min": -10,
"typ": null,
"max": 10,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Digital Input Voltage (Note 2)",
"symbol": "VIN",
"kind": "absolute_maximum",
"unit": "V",
"min": -0.3,
"typ": null,
"max": null,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Ambient Operating Temperature (Power Applied)",
"symbol": "TA",
"kind": "absolute_maximum",
"unit": "°C",
"min": -55,
"typ": null,
"max": 125,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Storage Temperature",
"symbol": "Tstg",
"kind": "absolute_maximum",
"unit": "°C",
"min": -65,
"typ": null,
"max": 150,
"conditions": "",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Power Supply Current - Unloaded (Note 3)",
"symbol": "ID",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": 12,
"max": 18,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); unloaded",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Power Dissipation - Unloaded (Note 3)",
"symbol": "PD",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": 40,
"max": 60,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); unloaded",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Input Leakage Current",
"symbol": "IIN",
"kind": "electrical",
"unit": "µA",
"min": -10,
"typ": null,
"max": 10,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade)",
"source_page": 7,
"source": "datasheet"
},
{
"name": "High-Level Input Voltage",
"symbol": "VIH",
"kind": "electrical",
"unit": "% VD",
"min": 70,
"typ": null,
"max": null,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade)",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Low-Level Input Voltage",
"symbol": "VIL",
"kind": "electrical",
"unit": "% VD",
"min": null,
"typ": null,
"max": 30,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade)",
"source_page": 7,
"source": "datasheet"
},
{
"name": "High-Level Output Voltage",
"symbol": "VOH",
"kind": "electrical",
"unit": "% VD",
"min": 80,
"typ": null,
"max": null,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); IOH = -1.2 mA",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Low-Level Output Voltage",
"symbol": "VOL",
"kind": "electrical",
"unit": "% VD",
"min": null,
"typ": null,
"max": 20,
"conditions": "VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); IOH = 1.2 mA",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 10)",
"symbol": "fXTAL",
"kind": "electrical",
"unit": "MHz",
"min": 8,
"typ": null,
"max": 14,
"conditions": "RefClkDiv[1:0] = 10; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 01)",
"symbol": "fXTAL",
"kind": "electrical",
"unit": "MHz",
"min": 16,
"typ": null,
"max": 28,
"conditions": "RefClkDiv[1:0] = 01; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 00)",
"symbol": "fXTAL",
"kind": "electrical",
"unit": "MHz",
"min": 32,
"typ": null,
"max": 50,
"conditions": "RefClkDiv[1:0] = 00; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Reference Clock Input Frequency (RefClkDiv[1:0] = 10)",
"symbol": "fREF_CLK",
"kind": "electrical",
"unit": "MHz",
"min": 8,
"typ": null,
"max": 14,
"conditions": "RefClkDiv[1:0] = 10; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Reference Clock Input Frequency (RefClkDiv[1:0] = 01)",
"symbol": "fREF_CLK",
"kind": "electrical",
"unit": "MHz",
"min": 16,
"typ": null,
"max": 28,
"conditions": "RefClkDiv[1:0] = 01; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Reference Clock Input Frequency (RefClkDiv[1:0] = 00)",
"symbol": "fREF_CLK",
"kind": "electrical",
"unit": "MHz",
"min": 32,
"typ": null,
"max": 56,
"conditions": "RefClkDiv[1:0] = 00; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Reference Clock Input Duty Cycle",
"symbol": "DREF_CLK",
"kind": "electrical",
"unit": "%",
"min": 45,
"typ": null,
"max": 55,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Internal System Clock Frequency",
"symbol": "fSYS_CLK",
"kind": "electrical",
"unit": "MHz",
"min": 8,
"typ": null,
"max": 14,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Input Frequency",
"symbol": "fCLK_IN",
"kind": "electrical",
"unit": "Hz (min) / MHz (max)",
"min": 50,
"typ": null,
"max": 30,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Input Pulse Width (fCLK_IN < fSYS_CLK/96)",
"symbol": "pwCLK_IN",
"kind": "timing",
"unit": "UI",
"min": 2,
"typ": null,
"max": null,
"conditions": "fCLK_IN < fSYS_CLK/96; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Input Pulse Width (fCLK_IN > fSYS_CLK/96)",
"symbol": "pwCLK_IN",
"kind": "timing",
"unit": "ns",
"min": 10,
"typ": null,
"max": null,
"conditions": "fCLK_IN > fSYS_CLK/96; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Skipping Timeout (Notes 5, 6)",
"symbol": "tCS",
"kind": "timing",
"unit": "ms",
"min": 20,
"typ": null,
"max": null,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Skipping Input Frequency (Note 6)",
"symbol": "fCLK_SKIP",
"kind": "electrical",
"unit": "Hz (min) / kHz (max)",
"min": 50,
"typ": null,
"max": 80,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "PLL Clock Output Frequency (Note 7)",
"symbol": "fCLK_OUT",
"kind": "electrical",
"unit": "MHz",
"min": 6,
"typ": null,
"max": 75,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "PLL Clock Output Duty Cycle (measured at VD/2)",
"symbol": "tOD",
"kind": "electrical",
"unit": "%",
"min": 45,
"typ": 50,
"max": 55,
"conditions": "Measured at VD/2; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Output Rise Time (20% to 80% of VD)",
"symbol": "tOR",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 1.7,
"max": 3,
"conditions": "20% to 80% of VD; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Clock Output Fall Time (80% to 20% of VD)",
"symbol": "tOF",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 1.7,
"max": 3,
"conditions": "80% to 20% of VD; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "PLL Lock Time - CLK_IN (fCLK_IN < 200 kHz) (Note 11)",
"symbol": "tLC",
"kind": "timing",
"unit": "UI",
"min": null,
"typ": 100,
"max": 200,
"conditions": "fCLK_IN < 200 kHz; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "PLL Lock Time - CLK_IN (fCLK_IN > 200 kHz) (Note 11)",
"symbol": "tLC",
"kind": "timing",
"unit": "ms",
"min": null,
"typ": 1,
"max": 3,
"conditions": "fCLK_IN > 200 kHz; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "PLL Lock Time - REF_CLK (fREF_CLK = 8 to 75 MHz)",
"symbol": "tLR",
"kind": "timing",
"unit": "ms",
"min": null,
"typ": 1,
"max": 3,
"conditions": "fREF_CLK = 8 to 75 MHz; CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Output Frequency Synthesis Resolution (High Resolution)",
"symbol": "ferr",
"kind": "tolerance",
"unit": "ppm",
"min": -0.5,
"typ": null,
"max": 0.5,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "Output Frequency Synthesis Resolution (High Multiplication)",
"symbol": "ferr",
"kind": "tolerance",
"unit": "ppm",
"min": -112,
"typ": null,
"max": 112,
"conditions": "CL = 15 pF; VD = 3.1–3.5 V; TA = -10 to +70 °C (Commercial)",
"source_page": 8,
"source": "datasheet"
},
{
"name": "SCL Clock Frequency",
"symbol": "fscl",
"kind": "timing",
"unit": "kHz",
"min": null,
"typ": null,
"max": 100,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Bus Free-Time Between Transmissions",
"symbol": "tbuf",
"kind": "timing",
"unit": "µs",
"min": 4.7,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Start Condition Hold Time (prior to first clock pulse)",
"symbol": "thdst",
"kind": "timing",
"unit": "µs",
"min": 4,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Clock Low Time",
"symbol": "tlow",
"kind": "timing",
"unit": "µs",
"min": 4.7,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Clock High Time",
"symbol": "thigh",
"kind": "timing",
"unit": "µs",
"min": 4,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Setup Time for Repeated Start Condition",
"symbol": "tsust",
"kind": "timing",
"unit": "µs",
"min": 4.7,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "SDA Setup Time to SCL Rising",
"symbol": "tsud",
"kind": "timing",
"unit": "ns",
"min": 250,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Rise Time of SCL and SDA",
"symbol": "tr",
"kind": "timing",
"unit": "µs",
"min": null,
"typ": null,
"max": 1,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Fall Time SCL and SDA",
"symbol": "tf",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": null,
"max": 300,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Setup Time for Stop Condition",
"symbol": "tsusp",
"kind": "timing",
"unit": "µs",
"min": 4.7,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Acknowledge Delay from SCL Falling",
"symbol": "tack",
"kind": "timing",
"unit": "ns",
"min": 300,
"typ": null,
"max": 1000,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "Delay from Supply Voltage Stable to Control Port Ready",
"symbol": "tdpor",
"kind": "timing",
"unit": "µs",
"min": 100,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 10,
"source": "datasheet"
},
{
"name": "CCLK Clock Frequency (SPI)",
"symbol": "fcclk",
"kind": "timing",
"unit": "MHz",
"min": null,
"typ": null,
"max": 6,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CCLK Edge to CS Falling (Note 14)",
"symbol": "tspi",
"kind": "timing",
"unit": "ns",
"min": 500,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CS High Time Between Transmissions",
"symbol": "tcsh",
"kind": "timing",
"unit": "µs",
"min": 1,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CS Falling to CCLK Edge",
"symbol": "tcss",
"kind": "timing",
"unit": "ns",
"min": 20,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CCLK Low Time",
"symbol": "tscl",
"kind": "timing",
"unit": "ns",
"min": 66,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CCLK High Time",
"symbol": "tsch",
"kind": "timing",
"unit": "ns",
"min": 66,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CDIN to CCLK Rising Setup Time",
"symbol": "tdsu",
"kind": "timing",
"unit": "ns",
"min": 40,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "CCLK Rising to DATA Hold Time (Note 15)",
"symbol": "tdh",
"kind": "timing",
"unit": "ns",
"min": 15,
"typ": null,
"max": null,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "Rise Time of CCLK and CDIN (Note 16)",
"symbol": "tr2",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": null,
"max": 100,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "Fall Time of CCLK and CDIN (Note 16)",
"symbol": "tf2",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": null,
"max": 100,
"conditions": "Logic 0 = GND; Logic 1 = VD; CL = 20 pF",
"source_page": 11,
"source": "datasheet"
},
{
"name": "Junction to Ambient Thermal Impedance (JEDEC 2-Layer)",
"symbol": "JA",
"kind": "thermal",
"unit": "°C/W",
"min": null,
"typ": null,
"max": 170,
"conditions": "",
"source_page": 35,
"source": "datasheet"
},
{
"name": "Junction to Ambient Thermal Impedance (JEDEC 4-Layer)",
"symbol": "JA",
"kind": "thermal",
"unit": "°C/W",
"min": null,
"typ": null,
"max": 100,
"conditions": "",
"source_page": 35,
"source": "datasheet"
}
]
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"cs2000cp-czzr"
],
"discovery_pitch": "CS2000CP-CZZR (Cirrus Logic) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cs2000cp-czzr.kicad_sym",
"cs2000cp-czzr.kicad_mod",
"cs2000cp-czzr.glb",
"cs2000cp-czzr.step",
"cs2000cp-czzr.lbr",
"docs/hero.png",
"docs/cs2000cp-czzr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cs2000cp-czzr-hero.glb",
"cs2000cp-czzr-hero.overlay.json",
"cs2000cp-czzr-etched.glb"
],
"visibility": {
"public": true
}
}