component

CS2000CP-CZZR

Public Made by Adom

by adom

Cirrus Logic Clock Generators / Frequency Synthesizers / PLL, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcs2000cp-czzrfactory-2.0.0extractor-text

Verified CS2000CP-CZZR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS2000CP-CZZR · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 37-page datasheet
  • •distributor (warn): no ['mouser'] number
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-q9o1dlnz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.35)
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs2000cp-czzr.kicad_sym✓ cs2000cp-czzr.kicad_mod✓ cs2000cp-czzr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cs2000cp-czzr: viewers · Ray
cs2000cp-czzr-etched.glb Publish 0.1.0 · Ray
cs2000cp-czzr-etched.step cs2000cp-czzr: factory component page (tier=lcsc) · Ray
cs2000cp-czzr-hero.glb cs2000cp-czzr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs2000cp-czzr-hero.overlay.json Publish 0.1.0 · Ray
cs2000cp-czzr.glb Publish 0.1.0 · Ray
cs2000cp-czzr.kicad_mod Publish 0.1.0 · Ray
cs2000cp-czzr.kicad_sym Publish 0.1.0 · Ray
cs2000cp-czzr.lbr Publish 0.1.0 · Ray
cs2000cp-czzr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 10 pins · Ray

CS2000CP-CZZR

Cirrus Logic · Clock Generators / Frequency Synthesizers / PLL · MSOP-10

CS2000CP-CZZR from Cirrus Logic, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VD power_in Positive power supply for the digital and analog sections of the device.
2 GND power_in Ground reference for the device.
3 CLK_OUT output PLL clock output, the output of the PLL clock path.
4 AUX_OUT output Buffered version of one of the input or output clocks, or a status signal, selected by register configuration.
5 CLK_IN input Clock input for the Digital PLL frequency reference.
6 XTO bidirectional Crystal connection pin used with XTI for an external crystal that generates the low-jitter PLL input clock.
7 XTI/REF_CLK bidirectional Crystal connection XTI (I/O for an external crystal) or timing reference clock input REF_CLK for an externally generated low-jitter reference clock.
8 AD0/CS input Address bit 0 (chip address pin) in I²C mode, and control port chip select signal in SPI mode.
9 SCL/CCLK input Serial clock for the serial control port in I²C and SPI mode.
10 SDA/CDIN bidirectional Serial data I/O line in I²C mode, and input data line for the control port interface in SPI mode.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package MSOP-10
Category RTC/Clock Chip
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Power Supply VD 3.1 3.3 3.5 V 7
Ambient Operating Temperature (Power Applied) Commercial Grade TAC -10 70 °C 7
DC Power Supply VD -0.3 6 V 7
Input Current IIN -10 10 mA 7
Digital Input Voltage (Note 2) VIN -0.3 V 7
Ambient Operating Temperature (Power Applied) TA -55 125 °C 7
Storage Temperature Tstg -65 150 °C 7
Power Supply Current - Unloaded (Note 3) ID 12 18 mA VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); unloaded 7
Power Dissipation - Unloaded (Note 3) PD 40 60 mW VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); unloaded 7
Input Leakage Current IIN -10 10 µA VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade) 7
High-Level Input Voltage VIH 70 % VD VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade) 7
Low-Level Input Voltage VIL 30 % VD VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade) 7
High-Level Output Voltage VOH 80 % VD VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); IOH = -1.2 mA 7
Low-Level Output Voltage VOL 20 % VD VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); IOH = 1.2 mA 7
Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 10) fXTAL 8 14 MHz RefClkDiv[1:0] = 10; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 01) fXTAL 16 28 MHz RefClkDiv[1:0] = 01; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Crystal Frequency, Fundamental Mode (RefClkDiv[1:0] = 00) fXTAL 32 50 MHz RefClkDiv[1:0] = 00; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Reference Clock Input Frequency (RefClkDiv[1:0] = 10) fREF_CLK 8 14 MHz RefClkDiv[1:0] = 10; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Reference Clock Input Frequency (RefClkDiv[1:0] = 01) fREF_CLK 16 28 MHz RefClkDiv[1:0] = 01; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Reference Clock Input Frequency (RefClkDiv[1:0] = 00) fREF_CLK 32 56 MHz RefClkDiv[1:0] = 00; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Reference Clock Input Duty Cycle DREF_CLK 45 55 % CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Internal System Clock Frequency fSYS_CLK 8 14 MHz CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Input Frequency fCLK_IN 50 30 Hz (min) / MHz (max) CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Input Pulse Width (fCLK_IN < fSYS_CLK/96) pwCLK_IN 2 UI fCLK_IN < fSYS_CLK/96; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Input Pulse Width (fCLK_IN > fSYS_CLK/96) pwCLK_IN 10 ns fCLK_IN > fSYS_CLK/96; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Skipping Timeout (Notes 5, 6) tCS 20 ms CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Skipping Input Frequency (Note 6) fCLK_SKIP 50 80 Hz (min) / kHz (max) CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
PLL Clock Output Frequency (Note 7) fCLK_OUT 6 75 MHz CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
PLL Clock Output Duty Cycle (measured at VD/2) tOD 45 50 55 % Measured at VD/2; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Output Rise Time (20% to 80% of VD) tOR 1.7 3 ns 20% to 80% of VD; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Clock Output Fall Time (80% to 20% of VD) tOF 1.7 3 ns 80% to 20% of VD; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
PLL Lock Time - CLK_IN (fCLK_IN < 200 kHz) (Note 11) tLC 100 200 UI fCLK_IN < 200 kHz; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
PLL Lock Time - CLK_IN (fCLK_IN > 200 kHz) (Note 11) tLC 1 3 ms fCLK_IN > 200 kHz; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
PLL Lock Time - REF_CLK (fREF_CLK = 8 to 75 MHz) tLR 1 3 ms fREF_CLK = 8 to 75 MHz; CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Output Frequency Synthesis Resolution (High Resolution) ferr -0.5 0.5 ppm CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
Output Frequency Synthesis Resolution (High Multiplication) ferr -112 112 ppm CL = 15 pF; VD = 3.1-3.5 V; TA = -10 to +70 °C (Commercial) 8
SCL Clock Frequency fscl 100 kHz Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Bus Free-Time Between Transmissions tbuf 4.7 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Start Condition Hold Time (prior to first clock pulse) thdst 4 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Clock Low Time tlow 4.7 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Clock High Time thigh 4 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Setup Time for Repeated Start Condition tsust 4.7 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
SDA Setup Time to SCL Rising tsud 250 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Rise Time of SCL and SDA tr 1 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Fall Time SCL and SDA tf 300 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Setup Time for Stop Condition tsusp 4.7 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Acknowledge Delay from SCL Falling tack 300 1000 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
Delay from Supply Voltage Stable to Control Port Ready tdpor 100 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 10
CCLK Clock Frequency (SPI) fcclk 6 MHz Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CCLK Edge to CS Falling (Note 14) tspi 500 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CS High Time Between Transmissions tcsh 1 µs Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CS Falling to CCLK Edge tcss 20 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CCLK Low Time tscl 66 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CCLK High Time tsch 66 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CDIN to CCLK Rising Setup Time tdsu 40 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
CCLK Rising to DATA Hold Time (Note 15) tdh 15 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
Rise Time of CCLK and CDIN (Note 16) tr2 100 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
Fall Time of CCLK and CDIN (Note 16) tf2 100 ns Logic 0 = GND; Logic 1 = VD; CL = 20 pF 11
Junction to Ambient Thermal Impedance (JEDEC 2-Layer) JA 170 °C/W 35
Junction to Ambient Thermal Impedance (JEDEC 4-Layer) JA 100 °C/W 35

CAD (KiCad official)

  • Symbol: CS2000CP-CZZR
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: cs2000cp-czzr-etched.step / cs2000cp-czzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs2000cp-czzr.step / cs2000cp-czzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (37 pp, sha256 c5a9b4f7822cfff6, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF