# CRSD082N10L2

**CRMICRO** · MOSFETs · TO-252

CRSD082N10L2 from CRMICRO, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage is limited to ±20 V absolute maximum, with a gate threshold of 1.4 to 2.2 V (1.8 V typ) at ID=250 µA. |
| 2 | D | passive | Drain, also connected to the exposed tab; drain-source voltage is 100 V maximum and continuous drain current is 78 A silicon-limited at TC=25°C. |
| 3 | S | passive | Source; connects to the body diode anode and is the return for the 78 A continuous (silicon limit) drain current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CRMICRO |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 100 | V |  | 1 |
| Continuous drain current (Silicon limit) | ID |  |  | 78 | A | TC = 25°C (Silicon limit) | 1 |
| Continuous drain current (Package limit) | ID |  |  | 80 | A | TC = 25°C (Package limit) | 1 |
| Continuous drain current (Silicon limit) | ID |  |  | 50 | A | TC = 100°C (Silicon limit) | 1 |
| Pulsed drain current | ID pulse |  |  | 313 | A | TC = 25°C, tp limited by Tjmax | 1 |
| Avalanche energy, single pulse | EAS |  |  | 121 | mJ | L=0.5mH, Rg=25Ω | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 1 |
| Power dissipation | Ptot |  |  | 101 | W | TC = 25°C | 1 |
| Operating junction and storage temperature | Tj, Tstg | -55 |  | 150 | °C |  | 1 |
| Thermal resistance, junction to case | RthJC |  |  | 1.24 | °C/W |  | 2 |
| Thermal resistance, junction to ambient | RthJA |  |  | 115 | °C/W | min. footprint | 2 |
| Drain-source breakdown voltage | BVDSS | 100 |  |  | V | VGS=0V, ID=250uA | 2 |
| Zero gate voltage drain current (Tj=25°C) | IDSS |  |  | 1 | µA | VDS=80V, VGS=0V, Tj=25°C | 2 |
| Zero gate voltage drain current (Tj=125°C) | IDSS |  |  | 10 | µA | VDS=80V, VGS=0V, Tj=125°C | 2 |
| Gate threshold voltage | VGS(th) | 1.4 | 1.8 | 2.2 | V | VDS=VGS, ID=250uA | 2 |
| Gate-source leakage current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 7.2 | 8.6 | mΩ | VGS=10V, ID=50A | 2 |
| Drain-source on-state resistance | RDS(on) |  | 9 | 10.8 | mΩ | VGS=4.5V, ID=50A | 2 |
| Body diode forward voltage | VSD |  | 0.93 | 1.4 | V | VGS=0V, ISD=50A | 3 |

## CAD (KiCad official)

- Symbol: `CRSD082N10L2`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files: `crsd082n10l2-etched.step` / `crsd082n10l2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `crsd082n10l2.step` / `crsd082n10l2.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CRMICRO datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893353018593280) (9 pp, sha256 `892a91af06714d94`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/crsd082n10l2-datasheet.pdf)