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codex / docs / FUSION-THERMAL-BOTTLENECKS.md
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John Lauer Update Fusion merge and thermal source status; retain native acceptance blocker 79e0bcf 28d ago

Astra reroutes around thermal bottlenecks

This pass starts from video 11's expanded BQ25792 board and changes routing to improve heat flow through the copper. The original board, candidate, failed search and actual native replay remain separate. No external autorouter was used.

N$1 (R9.2 to JP2.P1, input MOSFET control wiring) moves from the bottom to layer 15, removing the vertical cut through VAC1/VBUS. The VUSB supply branch moves to layer 15 at the same width/length. Five selected PGND connector segments move to layer 2. All transitions reuse existing plated pads/vias: adding more via holes was unnecessary. All 89 vias, components, footprint thermal holes, 12 pours, rule profile and stackup are preserved. SDA relocation searches, including a proposed two-via hop, did not find a valid candidate and were rejected; SDA stays unchanged.

Thermal net Connected bottom area before → after (mm²) Calculated bottom heat flow before → after (mW)
VAC1 / Q1 172.8 → 177.5 54.0 → 71.7 (+32.8%)
VBUS / Q2 + Q4 205.6 → 209.6 78.0 → 84.6 (+8.4%)
VAC2 / Q3 151.8 → 160.8 57.2 → 62.5 (+9.2%)
VBAT / Q5 235.4 → 235.4 94.2 → 94.2
PGND / IC1 + U2 275.2 → 275.2 79.8 → 79.8

These are geometry-derived areas and bottom-sheet model estimates, not measured board temperatures. Boundary conditions match the previous pass: source copper 65°C; ambient and radiative surroundings 25°C; copper 35 µm, conductivity 390 W/m/K; convection h=5 W/m²K; mask emissivity 0.8 and provisional mask film 25 µm/0.2 W/m/K. The model omits package/via resistance, FR4 and other-layer conduction, enclosure and simultaneous actual loads. It is not a junction prediction or allowable board power rating. Refining the mesh from 0.10 to 0.075 mm changes these four after-case heat flows by less than 1%; energy balance residuals are below 1e-6 W.

VAC1 gains only about 2.8% connected area but about 33% calculated heat flow: removing the bottleneck matters more than merely growing the outline. All four MOSFET regions together gain about 29.5 mW, or 10.4%, under the fixed boundary conditions. Solder mask remains unchanged.

Electrical tradeoffs remain explicit

N$1 grows from 14.32 to 26.71 mm. VUSB remains 4.83 mm; selected ground sections retain their lengths and 0.4 mm width. The N$1/VUSB sections retain 0.15 mm width; this pass does not establish an operating current rating. Their relocation consumes internal ground fill: layer 15 coverage decreases from 83.95% to 83.14%, while bottom coverage rises from 83.82% to 84.59%. The top layer is unchanged. Filled layer-2 PGND lies under about 89% of the N$1 centerline and 38% of VUSB's; this simple overlap screening does not establish a continuous high-frequency return path or signal-integrity signoff. VUSB is a supply, not the USB data pair. Actual gate transients, supply loads and assembly qualification remain necessary. Switching-node routes are unchanged.

Native replay validation

Fusion reports 583 segments, 89 vias, 12 pours, zero airwires, zero warnings and no new DRC errors. The inherited top-layer Copper Clearance error 5,1,f10227fd41e0ab5d remains. The same diagnostic rule profile as video 11 is used; this pass changes no rules. Native editing merges some collinear/overlapping same-net segments, so raw primitive counts differ from the XML candidate. Per-net copper unions on all four layers match exactly (symmetric-difference area below 1e-8 mm²). The accepted candidate has no off-angle segments above 0.02° tolerance. Copper refill and final Autodesk DRC were run on the actual recorded board.

Native calls: fusion_open_board, fusion_run_modeling_script, Electron.run RIPUP, LAYER, LINE ... +0, RATSNEST, DISPLAY, WINDOW, and SHOW. Routing-state and DRC helpers execute inside the modeling-script verb. AB's desktop_record_window_start/stop records the real Fusion window. The narrated edit uses 3x action, removed waits, explicit inspection holds and postproduction thermal plots.

Durable BRD/FBRD checkpoints were verified before the task's scratch document was closed. Fusion's isModified state and a successful source export are separate facts; the bridge now reminds callers about that lifecycle.

Reproduction status

Read eda-engineering, eda-electrical-routing, and eda-thermal-bottlenecks from the shared EDA Skillpack, plus the selected CAD bridge's skills. Discover your own desktop target and preserve user documents and pinned bridge builds. Use the previous expansion report and video 11 board as the baseline. The example scripts and accepted candidate are now published on Fusion Bridge master, merged through PR #8. This is source publication; inclusion in a later installable package and native installed-release acceptance remain separate checks. The shared EDA Skillpack is browseable source, not yet an installable package.

plan.py makes the candidate; hop.py preserves the rejected SDA experiment; validate.py imports, refills, runs DRC and checkpoints each candidate; compare.py/audit.py calculate thermal and geometric comparisons; record.py draws the accepted reroute natively; narration.py, charts.py, and render.py build the edit. These are BQ25792 example scripts, not a general-purpose autorouter. Configure the adjacent thermal/crr.example.py transport for your own host rather than copying private session details.

Primary thermal guidance: TI motor-driver board layout. Device role: TI BQ25792 datasheet.

Native board · EAGLE board source