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f7b1942
29d ago
Expanded thermal copper in Fusion — video 11
Astra expands the connected bottom heatsinks from video 10 while preserving every routed segment, via, component and layer. It reallocates available copper among VAC1, VBUS, VAC2, VBAT and PGND, then records native polygon creation and a highlighted tour of each net in Fusion on CRR. This is a constrained thermal-area experiment, not a proven globally optimal layout or a new autorouting run.
Result on the actual saved replay
| Thermal net | Before (mm²) | Expanded (mm²) | Before model (mW) | Expanded model (mW) |
|---|---|---|---|---|
| VAC1 | 28.1 | 172.8 | 12.1 | 54.0 |
| VBUS | 44.6 | 205.6 | 19.3 | 78.0 |
| VAC2 | 29.5 | 151.8 | 12.7 | 57.2 |
| VBAT | 24.4 | 235.4 | 10.4 | 94.2 |
Q1 uses VAC1; Q2/Q4 share VBUS; Q3 uses VAC2; Q5 uses VBAT. The four regions total 126.7 → 765.7 mm², about 6.0× the connected bottom area. Each FET retains its seven footprint thermal holes. Q2/Q4 share one region and are counted once. Thermal-pad net assignments are taken from the board, not inferred from the word “heatsink.”
The left notch reserves ground beneath U2, and the central ground corridor serves IC1. The bottom PGND area connected to their five added thermal vias falls from 928.0 to 275.2 mm². This is a real allocation tradeoff: the model's corresponding bottom ground heat path falls from 231 to 80 mW at the same imposed source temperature. Both internal ground pours remain unchanged. A load-weighted whole-board analysis could choose a different allocation; without actual component losses, the selected boundaries are an engineering candidate, not a universal best design.
Total bottom copper coverage is approximately 85.4% → 83.8% because the larger net partitions need isolation boundaries. Top and internal coverage stay unchanged. This is six times the useful MOSFET-connected area, not six times more metal, board cooling, or allowable current. SW1/SW2 geometry remains unchanged; enlarging high-dv/dt switching-node copper indiscriminately is inappropriate.
Native validation: 576 segments, 89 vias, 12 pours; zero off-angle segments; zero airwires; zero warnings; zero new DRC errors. One inherited top-layer copper clearance error remains, signature 5,1,f10227fd41e0ab5d. The inherited diagnostic same-net rule profile matches video 10; no additional rules were disabled. A first candidate with touching same-rank polygon boundaries produced two new clearance errors and was rejected. The accepted boundaries have separation, including 0.30 mm between the horizontal pour outlines. Native fill uses the existing clearance rules and 0.20 mm board-edge clearance.
The replay adds four larger polygons to the original eight; overlaps on the same net union to the same filled geometry as the eight-polygon analytical candidate. Exported connected regions agree within 0.0001 mm², and the route/via comparison is unchanged at six-decimal coordinate precision.
How the thermal estimate works
The table is an illustrative bottom-surface heat-path comparison, not measured heat and not a junction-temperature prediction. No actual operating current, ambient/enclosure or airflow was supplied for this run. The model uses:
- 35 µm copper, from the board's
mtCoppersetting; assumed conductivity 390 W/(m·K). - Bottom copper around the thermal holes held at 65°C; ambient air and radiative surroundings at 25°C. This is a boundary condition, not a measured device temperature.
- Convection coefficient 5 W/(m²·K), with sensitivity at 3 and 10.
- Provisional mask thickness 25 µm and conductivity 0.2 W/(m·K), to be replaced by the selected mask data.
- Emissivity 0.8 for mask, 0.05 for bright copper, 0.8 for oxidized copper, using Analog Devices' SOAtherm reference values. Real plating, oxidation, roughness and view factors change these values.
A 0.10 mm finite-difference grid follows the actual connected fill contours, pads and tracks. Adjacent cells conduct through the 35 µm copper sheet with per-square conductance k × thickness. Surface loss is calculated with convection and Stefan–Boltzmann radiation:
Qconv = h A (Ts - Ta)
Qrad = epsilon sigma A (Ts^4 - Ta^4) [temperatures in kelvin]
hr = epsilon sigma (Ts + Ta)(Ts^2 + Ta^2)
U = 1 / (1/(h + hr) + mask_thickness / mask_conductivity)
The solver iterates radiation with local copper temperature and integrates loss across the sheet. The thin mask film uses an approximate series resistance; ignoring that small correction changes little under these air-cooling assumptions. The 0.15 mm comparison grid changes expanded masked results by at most about 3.2%. Energy balance is checked, along with an analytical isothermal-sheet limit and an equal-area narrow-neck case. This is numerical checking, not physical validation. Fine copper connections, round pads and drill shapes are rasterized/approximated.
At the stated conditions, the MOSFET regions' bottom path grows from 0.0546 to 0.2834 W, an estimated 0.229 W difference. Varying convection from 3 to 10 gives 0.236–0.397 W for the expanded regions. These watts must not be added directly to an existing board power rating: package and via resistance, FR4 coupling, other copper layers, enclosure, neighboring component heat and actual simultaneous loads are omitted. The source-temperature constraint also assumes the thermal holes can deliver the needed heat; their resistance has not been declared zero in the real board.
Why the selected version keeps solder mask
For the same expanded geometry and nominal boundary conditions:
| Finish model | MOSFET-region bottom heat flow |
|---|---|
| Masked, epsilon 0.8 | 0.283 W |
| Half bright exposed, area-weighted approximation | 0.218 W |
| Fully bright exposed, epsilon 0.05 | 0.150 W |
| Oxidized exposed, epsilon 0.8 | 0.284 W |
The half-exposed case is an area-weighted emissivity illustration, not a shaped manufacturing mask opening or an actual ablation of the mask. Mask removal adds almost no surface area and the assumed thin coating contributes little resistance to still-air convection. Bright copper's lower radiation outweighs that small benefit. Keep the existing mask for this assumed air-cooled configuration. No large solder-mask openings were added. Oxidized copper's modeled similarity is not a reason to rely on uncontrolled oxidation. Real board pads already have manufacturing openings; the finish sweep idealizes the spreading region as a uniform surface.
An electrically appropriate heatsink or chassis interface is a different case: compare contact area, interface resistance, electrical isolation and corrosion/assembly requirements explicitly. Do not expose a VAC/VBUS/VBAT region for contact without designing that interface. The CSD17581Q3A datasheet also ties its thermal resistance examples to specified copper area and thickness; its test-board theta-JA is not this board's thermal resistance.
Reproduce and inspect
Install adom/codex, read codex-adom-electrical-routing and codex-adom-routing-video, and select your own live desktop. Preserve the previous board and pinned bridge. Source scripts and checks are on the adom/fusion-bridge branch feature/per-net-trace-routing, under demo/routing/bq25792/thermal-expansion/. Configure the adjacent thermal/crr.example.py transport for your discovered target; do not reuse this session's machine names, IDs or paths blindly.
Start with the video-10 saved board. Inventory component thermal nets and ground requirements; establish the load contract; propose allocation boundaries; native-refill each candidate; reject new DRC errors; measure actual connected copper; compare finish and heat-flow assumptions. For the exact historical replay, use the published board and expansion-03/bounds.json. For a fresh Astra design, recalculate boundaries using the actual component losses and fabrication contract.
The recorded operations use fusion_open_board, fusion_run_modeling_script, Electron.run POLYGON, CHANGE ISOLATE, CHANGE THERMALS, CHANGE ORPHANS, CHANGE RANK, RATSNEST, DISPLAY, WINDOW, and SHOW <net>. Snapshot/readback and routing_drc use the bridge's routing helper inside fusion_run_modeling_script; they are not invented top-level verbs. Document.CopyToDesktop saves the native FBRD. Adom Bridge's desktop_record_window_start/stop records the actual Fusion window. A terminal SHOW without a trailing semicolon keeps the net highlighted for the camera; verify its pixels after any snapshot or export, which can clear selection. Autodesk documents SHOW highlighting.
The video uses 3× action, removed waits, explicit inspection holds, postproduction numerical charts, and Adom TTS narration. Raw footage and edit timing remain in the workspace. Shared skills teach the general method; this worked example's figures are not acceptance targets for other boards.
Native FBRD · Exported BRD · Numerical results · Native audit
# Expanded thermal copper in Fusion — video 11
Astra expands the connected bottom heatsinks from video 10 while preserving every routed segment, via, component and layer. It reallocates available copper among VAC1, VBUS, VAC2, VBAT and PGND, then records native polygon creation and a highlighted tour of each net in Fusion on CRR. This is a constrained thermal-area experiment, not a proven globally optimal layout or a new autorouting run.
## Result on the actual saved replay
| Thermal net | Before (mm²) | Expanded (mm²) | Before model (mW) | Expanded model (mW) |
| --- | ---: | ---: | ---: | ---: |
| VAC1 | 28.1 | 172.8 | 12.1 | 54.0 |
| VBUS | 44.6 | 205.6 | 19.3 | 78.0 |
| VAC2 | 29.5 | 151.8 | 12.7 | 57.2 |
| VBAT | 24.4 | 235.4 | 10.4 | 94.2 |
Q1 uses VAC1; Q2/Q4 share VBUS; Q3 uses VAC2; Q5 uses VBAT. The four regions total **126.7 → 765.7 mm²**, about **6.0×** the connected bottom area. Each FET retains its seven footprint thermal holes. Q2/Q4 share one region and are counted once. Thermal-pad net assignments are taken from the board, not inferred from the word “heatsink.”
The left notch reserves ground beneath U2, and the central ground corridor serves IC1. The bottom PGND area connected to their five added thermal vias falls from **928.0 to 275.2 mm²**. This is a real allocation tradeoff: the model's corresponding bottom ground heat path falls from **231 to 80 mW** at the same imposed source temperature. Both internal ground pours remain unchanged. A load-weighted whole-board analysis could choose a different allocation; without actual component losses, the selected boundaries are an engineering candidate, not a universal best design.
Total bottom copper coverage is approximately **85.4% → 83.8%** because the larger net partitions need isolation boundaries. Top and internal coverage stay unchanged. This is six times the useful MOSFET-connected area, not six times more metal, board cooling, or allowable current. SW1/SW2 geometry remains unchanged; enlarging high-dv/dt switching-node copper indiscriminately is inappropriate.
**Native validation:** 576 segments, 89 vias, 12 pours; zero off-angle segments; zero airwires; zero warnings; zero new DRC errors. One inherited top-layer copper clearance error remains, signature `5,1,f10227fd41e0ab5d`. The inherited diagnostic same-net rule profile matches video 10; no additional rules were disabled. A first candidate with touching same-rank polygon boundaries produced two new clearance errors and was rejected. The accepted boundaries have separation, including 0.30 mm between the horizontal pour outlines. Native fill uses the existing clearance rules and 0.20 mm board-edge clearance.
The replay adds four larger polygons to the original eight; overlaps on the same net union to the same filled geometry as the eight-polygon analytical candidate. Exported connected regions agree within 0.0001 mm², and the route/via comparison is unchanged at six-decimal coordinate precision.
## How the thermal estimate works
The table is an illustrative **bottom-surface heat-path comparison**, not measured heat and not a junction-temperature prediction. No actual operating current, ambient/enclosure or airflow was supplied for this run. The model uses:
- 35 µm copper, from the board's `mtCopper` setting; assumed conductivity 390 W/(m·K).
- Bottom copper around the thermal holes held at 65°C; ambient air and radiative surroundings at 25°C. This is a boundary condition, not a measured device temperature.
- Convection coefficient 5 W/(m²·K), with sensitivity at 3 and 10.
- Provisional mask thickness 25 µm and conductivity 0.2 W/(m·K), to be replaced by the selected mask data.
- Emissivity 0.8 for mask, 0.05 for bright copper, 0.8 for oxidized copper, using [Analog Devices' SOAtherm reference values](https://www.analog.com/en/resources/technical-articles/ltspice-soatherm-support-for-pcb-and-heat-sink-thermal-models.html). Real plating, oxidation, roughness and view factors change these values.
A 0.10 mm finite-difference grid follows the actual connected fill contours, pads and tracks. Adjacent cells conduct through the 35 µm copper sheet with per-square conductance `k × thickness`. Surface loss is calculated with convection and Stefan–Boltzmann radiation:
```
Qconv = h A (Ts - Ta)
Qrad = epsilon sigma A (Ts^4 - Ta^4) [temperatures in kelvin]
hr = epsilon sigma (Ts + Ta)(Ts^2 + Ta^2)
U = 1 / (1/(h + hr) + mask_thickness / mask_conductivity)
```
The solver iterates radiation with local copper temperature and integrates loss across the sheet. The thin mask film uses an approximate series resistance; ignoring that small correction changes little under these air-cooling assumptions. The 0.15 mm comparison grid changes expanded masked results by at most about 3.2%. Energy balance is checked, along with an analytical isothermal-sheet limit and an equal-area narrow-neck case. This is numerical checking, not physical validation. Fine copper connections, round pads and drill shapes are rasterized/approximated.
At the stated conditions, the MOSFET regions' bottom path grows from **0.0546 to 0.2834 W**, an estimated **0.229 W** difference. Varying convection from 3 to 10 gives **0.236–0.397 W** for the expanded regions. These watts must not be added directly to an existing board power rating: package and via resistance, FR4 coupling, other copper layers, enclosure, neighboring component heat and actual simultaneous loads are omitted. The source-temperature constraint also assumes the thermal holes can deliver the needed heat; their resistance has not been declared zero in the real board.
## Why the selected version keeps solder mask
For the same expanded geometry and nominal boundary conditions:
| Finish model | MOSFET-region bottom heat flow |
| --- | ---: |
| Masked, epsilon 0.8 | 0.283 W |
| Half bright exposed, area-weighted approximation | 0.218 W |
| Fully bright exposed, epsilon 0.05 | 0.150 W |
| Oxidized exposed, epsilon 0.8 | 0.284 W |
The half-exposed case is an area-weighted emissivity illustration, not a shaped manufacturing mask opening or an actual ablation of the mask. Mask removal adds almost no surface area and the assumed thin coating contributes little resistance to still-air convection. Bright copper's lower radiation outweighs that small benefit. **Keep the existing mask for this assumed air-cooled configuration.** No large solder-mask openings were added. Oxidized copper's modeled similarity is not a reason to rely on uncontrolled oxidation. Real board pads already have manufacturing openings; the finish sweep idealizes the spreading region as a uniform surface.
An electrically appropriate heatsink or chassis interface is a different case: compare contact area, interface resistance, electrical isolation and corrosion/assembly requirements explicitly. Do not expose a VAC/VBUS/VBAT region for contact without designing that interface. The [CSD17581Q3A datasheet](https://www.ti.com/lit/gpn/CSD17581Q3A) also ties its thermal resistance examples to specified copper area and thickness; its test-board theta-JA is not this board's thermal resistance.
## Reproduce and inspect
Install `adom/codex`, read `codex-adom-electrical-routing` and `codex-adom-routing-video`, and select your own live desktop. Preserve the previous board and pinned bridge. Source scripts and checks are on the `adom/fusion-bridge` branch `feature/per-net-trace-routing`, under `demo/routing/bq25792/thermal-expansion/`. Configure the adjacent `thermal/crr.example.py` transport for your discovered target; do not reuse this session's machine names, IDs or paths blindly.
Start with the video-10 saved board. Inventory component thermal nets and ground requirements; establish the load contract; propose allocation boundaries; native-refill each candidate; reject new DRC errors; measure actual connected copper; compare finish and heat-flow assumptions. For the exact historical replay, use the published board and `expansion-03/bounds.json`. For a fresh Astra design, recalculate boundaries using the actual component losses and fabrication contract.
The recorded operations use `fusion_open_board`, `fusion_run_modeling_script`, `Electron.run POLYGON`, `CHANGE ISOLATE`, `CHANGE THERMALS`, `CHANGE ORPHANS`, `CHANGE RANK`, `RATSNEST`, `DISPLAY`, `WINDOW`, and `SHOW <net>`. Snapshot/readback and `routing_drc` use the bridge's routing helper inside `fusion_run_modeling_script`; they are not invented top-level verbs. `Document.CopyToDesktop` saves the native FBRD. Adom Bridge's `desktop_record_window_start/stop` records the actual Fusion window. A terminal `SHOW` without a trailing semicolon keeps the net highlighted for the camera; verify its pixels after any snapshot or export, which can clear selection. [Autodesk documents SHOW highlighting](https://help.autodesk.com/cloudhelp/ENU/Fusion-ECAD/files/ECD-CLI-S.htm).
The video uses 3× action, removed waits, explicit inspection holds, postproduction numerical charts, and Adom TTS narration. Raw footage and edit timing remain in the workspace. Shared skills teach the general method; this worked example's figures are not acceptance targets for other boards.
[Native FBRD](https://wiki.adom.inc/api/pages/adom/codex/files/boards/fusion/bq25792-expanded-thermal.fbrd) · [Exported BRD](https://wiki.adom.inc/api/pages/adom/codex/files/boards/fusion/bq25792-expanded-thermal.brd) · [Numerical results](https://wiki.adom.inc/api/pages/adom/codex/files/docs/fusion-thermal-expansion/thermal-results.json) · [Native audit](https://wiki.adom.inc/api/pages/adom/codex/files/docs/fusion-thermal-expansion/audit.json)