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29d ago
Electrical-aware PCB routing in Adom
Use Codex in Adom Hydrogen to inspect a public design, calculate routes, apply edits through KiCad Bridge, and validate the resulting copper in native KiCad. The objective is a board whose routing follows its electrical and manufacturing requirements. There is no universally ideal layout: loads, stackup, assembly and interfaces determine the tradeoffs.
This guide captures the methods developed during the public Adom Teazzers solenoid board experiment. The corresponding installed skill is codex-adom-electrical-routing. The new electrical-routing video is still being prepared; earlier videos demonstrate connectivity and live editing, not completed electrical qualification.
Start with a design contract
Read the schematic, PCB pad/net assignments, BOM, placement file and relevant manufacturer data. Record the source revision and preserve the human-routed original. Use a separate copy to strip and regenerate routing. Public permission must cover every board or image included in a shareable demo.
For this board, the user specifies 0.5 A per solenoid, accurate 0.1 mm ablation, supported vias, and optional 2 oz copper. We assume all five solenoids operate together: 2.5 A on the shared 24 V supply and return, plus the regulator input load. The current board file specifies 35 µm copper on each side and a 1.51 mm FR4 core. Optional heavier copper is not silently substituted into calculations.
The 0.1 mm value is a process capability. Current zone isolation remains 0.25 mm; its suitability still depends on voltage tolerance, transients, environment and manufacturing requirements. The external 5 V load remains unspecified. A component's advertised maximum rating does not establish the actual load.
For resistive loads, calculate current from the specified voltage and resistance when applicable. For solenoids, motors and external connector loads, establish operating current, duty cycle and simultaneous use. Sum downstream currents at shared trunks and ground returns. Converter input current depends on output power and efficiency.
Plan copper by electrical function
Reserve broad corridors for supply and load currents before routing ordinary signals. Keep the regulator switch node compact and its current loop short. Give quiet signals an uninterrupted reference plane. Route USB as a pair with controlled geometry and short transitions; do not independently optimize its two nets and then compare total copper lengths.
Unused space can become connected ground. Power pours can retain useful copper and reduce resistance. Explicit priorities partition overlapping zone outlines. Remove floating islands unless the fabrication and electrical specification explicitly permits them. Large switching-node pours can increase coupling, so maximizing every net's area is not a valid general rule.
Inspect all bottlenecks: pad escapes, narrow passages between foreign pads, thermal spokes, vias, connector contacts and shared return paths. Copper area alone does not establish current capacity. Measure resistance and voltage drop using the actual thickness and geometry; thermal estimates also need mounting and cooling assumptions. Verify manufactured hardware at its intended load.
What the experiment taught us
| Observation | Applied method | Acceptance evidence |
|---|---|---|
| Search-grid routing produced many bends | Simplify degree-two chains while preserving pads, branches and vias; check shortcuts against other copper | 1,463 segments reduced to 596 before later edits; native connectivity retained |
| New power territories split existing ground | Inspect actual filled islands and add plated ground stitching where both layers provide safe landing copper | Ground connectivity restored after refill |
| A connector ground pad had one thermal spoke instead of two | Rotate that pad's thermal spokes by 45 degrees | Native starved-thermal error disappeared without lowering the required spoke count |
| Large load-zone outlines hid inadequate connectivity | On a diagnostic copy, remove all 158 supply/drain trace segments and refill | Initial result exposed six 24 V opens and five thermal errors |
| Drain regions surrounded neighboring supply pads | Narrow the drain territory near connector supply pads and extend the input supply region | Pours alone connect the 24 V and five drain nets; zero unconnected items |
| A schematic LED was missing from the PCB | Restore the matching LED footprint/net assignments and recalculate the conflicting reset route | Native clearance and connectivity checks passed |
| Broad copper looked impressive but lacked a measurement | Measure actual native filled polygons separately for each layer | 79.73% front and 86.67% back filled-zone coverage at this checkpoint |
The current checkpoint has 95 footprints, 444 trace segments and 46 vias. Native refill/DRC reports zero unconnected items and two errors, both inherited connector courtyard overlaps. There are also warnings; this is not a zero-violation board. The BOM/CPL lists J202/J204 while J201/J203 are overlapping alternate terminal-block footprints; confirm the assembly variant rather than globally disabling courtyard checks.
These coverage percentages count filled zones only. For a total retained-copper metric, union zone, pad and trace polygons within the board boundary to avoid double-counting. Laser time also depends on contour length, passes and travel, so a copper percentage is not a machining-time claim.
Electrical findings that geometry cannot settle
The TI LM2596 datasheet specifies the switching layout requirements and permits its ON/OFF input to remain open for operation. An ERC undriven-input warning therefore needs interpretation against the device specification.
The fitted Bourns SRR1260-470M inductor lists 2.60 A maximum RMS current and 2.50 A typical saturation current. An ideal 24-to-5 V, 47 µH, 150 kHz calculation gives roughly 0.56 A peak-to-peak ripple. This does not support claiming a guaranteed 3 A output merely because the regulator is advertised as 3 A. Establish the actual 5 V load and check worst-case inductance, ripple, temperature and peak current.
The Nexperia PSMN1R2-30YLD is a 30 V MOSFET with specified on-resistance at 4.5 V gate drive. A nominal 24 V supply and 3.3 V logic drive require explicit transient and gate-drive review. The public board uses low-side switches. Do not copy contradictory high-side terminology from a wiki overview.
The RP2040 hardware-design guide provides USB layout guidance. The board also exposes USB through machine contacts, creating additional branches. Total net copper length is not an endpoint path length or pair skew. Interface usage and branch geometry must be checked alongside the pair and reference plane.
Repeatable execution and evidence
- Run the Adom context entry point; discover the target, active board, runtime and development pin. Use background operations during development.
- Capture source, schematic/BOM parity, native baseline DRC and fabrication/load assumptions.
- Calculate geometry from pads and nets. Keep source reference copper out of replacement path planning when demonstrating independent routing.
- Apply revision-checked
kicad_route_netedits and use the discovered removal/state/validation verbs. Discover current schemas instead of copying stale arguments. - Refill and run native DRC on disposable closed files for experiments. Inspect nested Bridge errors and native process exit status. Never headlessly save a file that the GUI is editing.
- Reject shorts and new clearance/thermal failures. Record failed candidates and why they failed. Re-check power connectivity independently of thin parallel traces.
- Measure the accepted board, then repeat validation on the actual live replay. Capture original-board tour, visible wipe and route/pour construction through window recording.
- Narrate the load choices, routing decisions, measurements and remaining limits. Disclose precomputation and 3× edited playback. Use Adom TTS and deliver the video to the selected desktop player.
The implementation currently combines custom Python geometry/visibility/A* planning, KiCad Bridge trace edits and native KiCad zone/refill operations. It does not use Freerouting. This is an evolving explicit planner and validation workflow, not proof of a universal production autorouter.
Keep improving the shared package
Save reusable lessons in the skill and worked examples in this guide. Keep private boards, host paths, session IDs and machine-specific state out of shared assets. Publish a new package tarball as well as wiki source; verify the installer and installed skill hashes. Existing conversations must explicitly read new skills; a fresh conversation is needed to test automatic skill discovery.
Cleaner geometry and thermal review before routing
The next refinement adopts horizontal and vertical runs with 45-degree transitions as the default. The numerical audit found 14 arbitrary-angle segments in the previous checkpoint; all were replaced with orthogonal/45-degree geometry, and ten exact duplicate segments were removed. Native refill preserved zero unconnected items and the two inherited connector-overlap errors. Curved, tangent native tracks remain an optional future style; this example uses 45-degree transitions.
Thermal planning starts by identifying the regulator, MOSFETs, catch/flyback diodes, inductor, exposed pads and existing via structures. The regulator's large tab is GND; the five MOSFET mounting pads are their respective drain nets. Those assignments matter when spreading heat across copper. The current two-layer board has no inner routing layers, so this example preserves the existing stackup.
For U201, the new candidate adds a local ground spreader and ten 0.60 mm / 0.30 mm drill ground vias beside the solder land to connect with back-layer ground. Placing them beside the land avoids introducing open holes directly into the tab's solder area. The first oversized region disrupted a connector path; reserving that corridor restored connectivity. The final candidate retains the compact regulator switching node and the separately assigned MOSFET drain copper. These changes provide a physical heat-spreading path; they do not constitute a measured junction-temperature improvement.
A native KiCad detail uncovered during this work: deliberately assigned stitching/thermal vias can have their nets reassigned during refill when old fill geometry is present. Preserve their intended net using native free-via semantics where appropriate, refill, and read back actual net assignments; a file's requested net is not sufficient proof. Check clearances and connectivity again after this correction.
For another board, calculate device losses and consult manufacturer thermal layouts before choosing copper area or via patterns. Use inner routing layers to preserve external heat-spreading copper only when those layers exist in the selected stackup and their reference planes remain suitable. Preserve airflow, mechanical and assembly constraints. The TI LM2596 thermal guidance and Nexperia device pinning/thermal data informed this example.
# Electrical-aware PCB routing in Adom
Use Codex in Adom Hydrogen to inspect a public design, calculate routes, apply edits through KiCad Bridge, and validate the resulting copper in native KiCad. The objective is a board whose routing follows its electrical and manufacturing requirements. There is no universally ideal layout: loads, stackup, assembly and interfaces determine the tradeoffs.
This guide captures the methods developed during the public [Adom Teazzers solenoid board](https://wiki.adom.inc/adom/teazzers-solenoid-driver-rp2040-v1-1) experiment. The corresponding installed skill is `codex-adom-electrical-routing`. The new electrical-routing video is still being prepared; earlier videos demonstrate connectivity and live editing, not completed electrical qualification.
## Start with a design contract
Read the schematic, PCB pad/net assignments, BOM, placement file and relevant manufacturer data. Record the source revision and preserve the human-routed original. Use a separate copy to strip and regenerate routing. Public permission must cover every board or image included in a shareable demo.
For this board, the user specifies 0.5 A per solenoid, accurate 0.1 mm ablation, supported vias, and optional 2 oz copper. We assume all five solenoids operate together: 2.5 A on the shared 24 V supply and return, plus the regulator input load. The current board file specifies 35 µm copper on each side and a 1.51 mm FR4 core. Optional heavier copper is not silently substituted into calculations.
The 0.1 mm value is a process capability. Current zone isolation remains 0.25 mm; its suitability still depends on voltage tolerance, transients, environment and manufacturing requirements. The external 5 V load remains unspecified. A component's advertised maximum rating does not establish the actual load.
For resistive loads, calculate current from the specified voltage and resistance when applicable. For solenoids, motors and external connector loads, establish operating current, duty cycle and simultaneous use. Sum downstream currents at shared trunks and ground returns. Converter input current depends on output power and efficiency.
## Plan copper by electrical function
Reserve broad corridors for supply and load currents before routing ordinary signals. Keep the regulator switch node compact and its current loop short. Give quiet signals an uninterrupted reference plane. Route USB as a pair with controlled geometry and short transitions; do not independently optimize its two nets and then compare total copper lengths.
Unused space can become connected ground. Power pours can retain useful copper and reduce resistance. Explicit priorities partition overlapping zone outlines. Remove floating islands unless the fabrication and electrical specification explicitly permits them. Large switching-node pours can increase coupling, so maximizing every net's area is not a valid general rule.
Inspect all bottlenecks: pad escapes, narrow passages between foreign pads, thermal spokes, vias, connector contacts and shared return paths. Copper area alone does not establish current capacity. Measure resistance and voltage drop using the actual thickness and geometry; thermal estimates also need mounting and cooling assumptions. Verify manufactured hardware at its intended load.
## What the experiment taught us
| Observation | Applied method | Acceptance evidence |
| --- | --- | --- |
| Search-grid routing produced many bends | Simplify degree-two chains while preserving pads, branches and vias; check shortcuts against other copper | 1,463 segments reduced to 596 before later edits; native connectivity retained |
| New power territories split existing ground | Inspect actual filled islands and add plated ground stitching where both layers provide safe landing copper | Ground connectivity restored after refill |
| A connector ground pad had one thermal spoke instead of two | Rotate that pad's thermal spokes by 45 degrees | Native starved-thermal error disappeared without lowering the required spoke count |
| Large load-zone outlines hid inadequate connectivity | On a diagnostic copy, remove all 158 supply/drain trace segments and refill | Initial result exposed six 24 V opens and five thermal errors |
| Drain regions surrounded neighboring supply pads | Narrow the drain territory near connector supply pads and extend the input supply region | Pours alone connect the 24 V and five drain nets; zero unconnected items |
| A schematic LED was missing from the PCB | Restore the matching LED footprint/net assignments and recalculate the conflicting reset route | Native clearance and connectivity checks passed |
| Broad copper looked impressive but lacked a measurement | Measure actual native filled polygons separately for each layer | 79.73% front and 86.67% back filled-zone coverage at this checkpoint |
The current checkpoint has 95 footprints, 444 trace segments and 46 vias. Native refill/DRC reports zero unconnected items and two errors, both inherited connector courtyard overlaps. There are also warnings; this is not a zero-violation board. The BOM/CPL lists J202/J204 while J201/J203 are overlapping alternate terminal-block footprints; confirm the assembly variant rather than globally disabling courtyard checks.
These coverage percentages count filled zones only. For a total retained-copper metric, union zone, pad and trace polygons within the board boundary to avoid double-counting. Laser time also depends on contour length, passes and travel, so a copper percentage is not a machining-time claim.
## Electrical findings that geometry cannot settle
The [TI LM2596 datasheet](https://www.ti.com/lit/ds/symlink/lm2596.pdf) specifies the switching layout requirements and permits its ON/OFF input to remain open for operation. An ERC undriven-input warning therefore needs interpretation against the device specification.
The fitted [Bourns SRR1260-470M inductor](https://www.bourns.com/docs/product-datasheets/srr1260.pdf) lists 2.60 A maximum RMS current and 2.50 A typical saturation current. An ideal 24-to-5 V, 47 µH, 150 kHz calculation gives roughly 0.56 A peak-to-peak ripple. This does not support claiming a guaranteed 3 A output merely because the regulator is advertised as 3 A. Establish the actual 5 V load and check worst-case inductance, ripple, temperature and peak current.
The [Nexperia PSMN1R2-30YLD](https://assets.nexperia.com/documents/data-sheet/PSMN1R2-30YLD.pdf) is a 30 V MOSFET with specified on-resistance at 4.5 V gate drive. A nominal 24 V supply and 3.3 V logic drive require explicit transient and gate-drive review. The public board uses low-side switches. Do not copy contradictory high-side terminology from a wiki overview.
The [RP2040 hardware-design guide](https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf) provides USB layout guidance. The board also exposes USB through machine contacts, creating additional branches. Total net copper length is not an endpoint path length or pair skew. Interface usage and branch geometry must be checked alongside the pair and reference plane.
## Repeatable execution and evidence
1. Run the Adom context entry point; discover the target, active board, runtime and development pin. Use background operations during development.
2. Capture source, schematic/BOM parity, native baseline DRC and fabrication/load assumptions.
3. Calculate geometry from pads and nets. Keep source reference copper out of replacement path planning when demonstrating independent routing.
4. Apply revision-checked `kicad_route_net` edits and use the discovered removal/state/validation verbs. Discover current schemas instead of copying stale arguments.
5. Refill and run native DRC on disposable closed files for experiments. Inspect nested Bridge errors and native process exit status. Never headlessly save a file that the GUI is editing.
6. Reject shorts and new clearance/thermal failures. Record failed candidates and why they failed. Re-check power connectivity independently of thin parallel traces.
7. Measure the accepted board, then repeat validation on the actual live replay. Capture original-board tour, visible wipe and route/pour construction through window recording.
8. Narrate the load choices, routing decisions, measurements and remaining limits. Disclose precomputation and 3× edited playback. Use Adom TTS and deliver the video to the selected desktop player.
The implementation currently combines custom Python geometry/visibility/A* planning, KiCad Bridge trace edits and native KiCad zone/refill operations. It does not use Freerouting. This is an evolving explicit planner and validation workflow, not proof of a universal production autorouter.
## Keep improving the shared package
Save reusable lessons in the skill and worked examples in this guide. Keep private boards, host paths, session IDs and machine-specific state out of shared assets. Publish a new package tarball as well as wiki source; verify the installer and installed skill hashes. Existing conversations must explicitly read new skills; a fresh conversation is needed to test automatic skill discovery.
## Cleaner geometry and thermal review before routing
The next refinement adopts horizontal and vertical runs with 45-degree transitions as the default. The numerical audit found 14 arbitrary-angle segments in the previous checkpoint; all were replaced with orthogonal/45-degree geometry, and ten exact duplicate segments were removed. Native refill preserved zero unconnected items and the two inherited connector-overlap errors. Curved, tangent native tracks remain an optional future style; this example uses 45-degree transitions.
Thermal planning starts by identifying the regulator, MOSFETs, catch/flyback diodes, inductor, exposed pads and existing via structures. The regulator's large tab is GND; the five MOSFET mounting pads are their respective drain nets. Those assignments matter when spreading heat across copper. The current two-layer board has no inner routing layers, so this example preserves the existing stackup.
For U201, the new candidate adds a local ground spreader and ten 0.60 mm / 0.30 mm drill ground vias beside the solder land to connect with back-layer ground. Placing them beside the land avoids introducing open holes directly into the tab's solder area. The first oversized region disrupted a connector path; reserving that corridor restored connectivity. The final candidate retains the compact regulator switching node and the separately assigned MOSFET drain copper. These changes provide a physical heat-spreading path; they do not constitute a measured junction-temperature improvement.
A native KiCad detail uncovered during this work: deliberately assigned stitching/thermal vias can have their nets reassigned during refill when old fill geometry is present. Preserve their intended net using native free-via semantics where appropriate, refill, and read back actual net assignments; a file's requested net is not sufficient proof. Check clearances and connectivity again after this correction.
For another board, calculate device losses and consult manufacturer thermal layouts before choosing copper area or via patterns. Use inner routing layers to preserve external heat-spreading copper only when those layers exist in the selected stackup and their reference planes remain suitable. Preserve airflow, mechanical and assembly constraints. The [TI LM2596 thermal guidance](https://www.ti.com/lit/ds/symlink/lm2596.pdf) and [Nexperia device pinning/thermal data](https://assets.nexperia.com/documents/data-sheet/PSMN1R2-30YLD.pdf) informed this example.