Codex

@@ -66,3 +66,15 @@ The implementation currently combines custom Python geometry/visibility/A* plann ## Keep improving the shared package  Save reusable lessons in the skill and worked examples in this guide. Keep private boards, host paths, session IDs and machine-specific state out of shared assets. Publish a new package tarball as well as wiki source; verify the installer and installed skill hashes. Existing conversations must explicitly read new skills; a fresh conversation is needed to test automatic skill discovery.++## Cleaner geometry and thermal review before routing++The next refinement adopts horizontal and vertical runs with 45-degree transitions as the default. The numerical audit found 14 arbitrary-angle segments in the previous checkpoint; all were replaced with orthogonal/45-degree geometry, and ten exact duplicate segments were removed. Native refill preserved zero unconnected items and the two inherited connector-overlap errors. Curved, tangent native tracks remain an optional future style; this example uses 45-degree transitions.++Thermal planning starts by identifying the regulator, MOSFETs, catch/flyback diodes, inductor, exposed pads and existing via structures. The regulator's large tab is GND; the five MOSFET mounting pads are their respective drain nets. Those assignments matter when spreading heat across copper. The current two-layer board has no inner routing layers, so this example preserves the existing stackup.++For U201, the new candidate adds a local ground spreader and ten 0.60 mm / 0.30 mm drill ground vias beside the solder land to connect with back-layer ground. Placing them beside the land avoids introducing open holes directly into the tab's solder area. The first oversized region disrupted a connector path; reserving that corridor restored connectivity. The final candidate retains the compact regulator switching node and the separately assigned MOSFET drain copper. These changes provide a physical heat-spreading path; they do not constitute a measured junction-temperature improvement.++A native KiCad detail uncovered during this work: deliberately assigned stitching/thermal vias can have their nets reassigned during refill when old fill geometry is present. Preserve their intended net using native free-via semantics where appropriate, refill, and read back actual net assignments; a file's requested net is not sufficient proof. Check clearances and connectivity again after this correction.++For another board, calculate device losses and consult manufacturer thermal layouts before choosing copper area or via patterns. Use inner routing layers to preserve external heat-spreading copper only when those layers exist in the selected stackup and their reference planes remain suitable. Preserve airflow, mechanical and assembly constraints. The [TI LM2596 thermal guidance](https://www.ti.com/lit/ds/symlink/lm2596.pdf) and [Nexperia device pinning/thermal data](https://assets.nexperia.com/documents/data-sheet/PSMN1R2-30YLD.pdf) informed this example.

@@ -20,6 +20,16 @@ Classify nets before optimizing geometry: - USB and other differential signals: route as a pair using the actual stackup, controlled spacing and a continuous return plane. Check stubs, branches, via transitions and endpoint constraints. Total net copper length is not the end-to-end pair skew. - Ordinary signals: prefer short, consistent-width paths and few intentional bends. Smooth search-grid stair steps only when clearance and connectivity remain verified. +# Routing appearance and thermal planning++Default to horizontal and vertical runs joined by 45-degree transitions. Optimize the number of bends and vias as well as route length; do not leave arbitrary-angle links or search-grid stair steps just because they pass DRC. Preserve intentional pad escapes, component rotations, differential spacing and electrical constraints. Audit segment angles numerically, then inspect the actual board visually. Report any exceptions rather than claiming every segment is orthogonal/45-degree. Smooth tangent arcs are an optional alternative when the native CAD API, clearances and fabrication process support them; use actual native arcs and verify their radius and tangency rather than approximating curves with many tiny segments.++Before allocating routes and pours, inventory heat-producing and high-current components, exposed pads, heatsink tabs, existing thermal-via arrays and thermal features embedded in footprints. Determine each thermal pad's electrical net from the schematic and manufacturer data; do not assume an exposed pad or heatsink tab is ground. Estimate relevant conduction, switching and regulator losses under the load contract and document uncertainty.++Reserve useful connected copper beneath and around those parts, and connect to an appropriate opposite-side or internal spreading region with deliberate thermal vias where supported. Preserve existing thermal vias and understand their net and assembly purpose before altering them. Check via drill/plating, pitch, solder wicking and whether filled/capped vias are required. A thermal pad's solid connection may matter more than total board copper area. Use available external copper for heat spreading while preserving routing corridors, return planes and manufacturer keepouts; do not enlarge a high-dv/dt switching node indiscriminately.++Where the existing stackup has inner layers, consider routing suitable signals there to preserve external heat-spreading copper, while maintaining their reference planes and power paths. Do not invent inner layers on a two-layer board or change the stackup without a design decision. External copper can improve heat transfer, but bottom-side cooling is not automatically best: enclosure, airflow, mounting, insulation and contact surfaces determine the benefit. Quantify improvements where supported; copper area alone is not a junction-temperature result.+ # Copper retention for ablation  When the fabrication goal is to remove as little copper as possible, optimize the actual filled copper area on each layer inside the permitted board boundary. Broad power regions can lower resistance; connected ground can occupy unused space and support return paths. Do not give every net an unrestricted board-wide pour. Partition by electrical function, reserve isolation/return corridors, and use explicit zone priorities.