Codex
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8e8cb8c
28d ago
BMS: revisited copper, 3D X-ray and calculated current density
Kale's original board is on the left; Astra's revised copy is on the right. This review revisits the loss of the 3.3 V plane and the reduced interlayer connections exposed by the previous comparison. It preserves the original and previous Astra board as separate checkpoints. These films are derived native-board analysis graphics and inspection holds, not a recording of fresh live routing.
The narrated review begins at the board file's actual layer spacing, then separates the four layers by 23.6 times for visibility. Inactive copper is 85% transparent; selected copper with a path to a circuit pad is opaque. Muted blue identifies selected-net regions without a pad path. Plated interlayer connections are drawn vertically. Both boards use the same camera, orientation and scale.
Inspect all 236 nets
This silent 15:44 atlas holds each matched net for four seconds in a stacked X-ray comparison. It contains no current-density overlay. A nominal zone net name is not proof that an orphan island joins that circuit. The narrative film applies current colors only to the two explicitly modeled load cases below.
What changed
The 3.3 V region on In2.Cu grows from 4.49 mm² in the previous Astra board to 1079.95 mm², compared with 1060.66 mm² on Kale's board. Of the revised inner-layer supply copper, 816.96 mm² has a geometric path to circuit pads and 262.99 mm² is retained but floating. This restores a supply-plane candidate; it also reallocates QGND copper on that layer, so it is not proof of equivalent reference continuity or impedance. Footprints, pad positions and net membership are unchanged.
The revision adds 48 power-path through vias: 24 on the shared drain, 12 on PACK+, and 12 on FBAT. They have 0.6 mm diameter and 0.3 mm drill. Placement was checked against fixed other-net copper, followed by native refill and DRC. A second audit added another 52 supply/reference stitches: one 3.3 V via, 23 VSS, 16 PGND and 12 QGND. This reduced nominal-net copper with no pad path from about 5382 to 2120 mm² in the geometric audit. Existing electrical clearances were not reduced. Via plating and assembly treatment still need manufacturing confirmation.
The user explicitly permits orphaned pours to reduce copper ablation. The revision retains them within the existing clearances and keepouts. Copper assigned to sensitive switching or isolation regions still needs functional review; no floating island receives load-current credit simply because it has a zone net label.
| Board | F.Cu mm² | In1.Cu mm² | In2.Cu mm² | B.Cu mm² | Total mm² |
|---|---|---|---|---|---|
| Kale original | 9674.0 | 11295.6 | 9092.6 | 8116.4 | 38178.6 |
| Previous Astra | 8883.7 | 9799.0 | 8875.7 | 8917.9 | 36476.2 |
| Astra revisited | 9569.4 | 10128.6 | 9692.6 | 9671.0 | 39061.6 |
Totals union all refilled conductor geometry, including pads, tracks, vias and assigned graphics, subtract drill voids, and clip to the board. The revised total is 7.09% above the prior Astra candidate and 2.31% above Kale, including retained floating copper. Projected area is not laser time or thermal performance.
Current density, not temperature
The first-order DC model uses 35 µm copper at 20°C, with the 100% IACS reference resistivity, and provisional 25 µm via plating. Copper-center spacing is 0.508186 mm from the board file. Source/sink contacts are ideal equipotential regions. The solver distributes current through planar copper and resistive plated barrels; it does not impose equal current per pin or layer.
- CD: 6 A between populated Q8 drain pads 5–9 and Q9 drain pads 5–9. DNP devices receive no source or assumed parallel conduction.
- PACK+: 6 A between Q9 source pads 1–3 and the combined front annuli of MC25/MC26. This is a specified comparison boundary condition, not a verified connector assembly or contact-resistance model.
| Calculated copper-only drop at 6 A | Kale | Previous Astra | Revised Astra |
|---|---|---|---|
| Shared drain, 0.1 mm mesh | 3.54 mV | 3.08 mV | 2.42 mV |
| PACK+, 0.075 mm mesh | 6.05 mV | Not evaluated in this revision | 4.27 mV |
These are provisional coupon-like conductor calculations. They omit solder/contact and package resistance, temperature feedback, switching, inductance and external wiring. They do not establish full pack voltage drop, a current rating, junction temperature or a qualified design.
The paired drain maps share a 0–40 A/mm² scale, with values above 40 saturated red. PACK+ uses 0–80 A/mm², with values above 80 saturated red. Colors show in-plane current density, not barrel current or temperature. Small contacts can concentrate current even when the surrounding pour is broad. The raw corner/contact maxima changed substantially on mesh refinement and are deliberately not promoted as precise physical peak values.
Current and power balance residuals are below 1e-8 relative in the documented solves. A rectangular discrete conductor matches its analytical resistance to better than 1e-8 relative. Halving the drain mesh from 0.2 to 0.1 mm and PACK+ from 0.15 to 0.075 mm changes the compared effective resistances by under 3%. This supports the observed resistance trend, not convergence of local maxima. Varying revised drain via plating from 18 to 35 µm changes its calculated drop from about 2.49 to 2.36 mV. Other fabrication and contact uncertainties remain.
Native validation, with the actual findings
The retained-island board reports 199 isolated-copper warnings and one zone-to-zone connection error under the inherited rules. It is not described as a zero-open board. A separate diagnostic copy with island removal enabled reports zero opens and zero violations, supporting classification of that retained-board connection report as island-related rather than a lost pad connection.
With ignored keepout, mask and dangling-via checks enabled on preserved comparison copies, Kale reports four keepout findings, 71 mask items and 12 dangling-via warnings. The revision reports four keepout findings, 81 mask items, 199 island warnings and the one zone connection error. All revised mask items identify the existing E1–E6 spark-gap apertures; none identifies a new via or another aperture. The increased item count remains disclosed and those features require assembly/electrical review. No rules were suppressed to improve this result.
Removing islands can let other nets refill the vacated area, so subtracting two refills is not an exact floating-area measurement. The analysis separately classifies conductor components on the actual retained board by paths through plated holes to circuit pads. A path to any pad is different from membership in an active 6 A load case.
How Adom makes it reproducible
Codex Astra in Adom Hydrogen planned the changes. Adom Bridge's explicit-target run_script calls ran native KiCad Python edits, refill, uncapped CLI DRC and exports on ConfRoomROG. kicad_status verified the installed test runtime, KiCad Bridge 0.9.347 with KiCad 10.0.5. pull_file transferred native evidence back for analysis. The numerical solve and 3D rendering ran separately in the container. No external autorouter was used, and this revision is not presented as live per-trace replay.
General guidance is included in the adom/codex 0.1.22 package, in codex-adom-electrical-routing and its references/multilayer-current-review.md, with an ablation-skill cross-reference. It teaches preserved checkpoints, matched net highlights, actual versus exploded layer spacing, explicit electrical boundary conditions, convergence checks, orphan classification, native validation and honest narration. It does not impose this BMS's 6 A load or via assumptions on another board. Install or update the package, then start a fresh Codex session to load its catalog; an existing thread can read the installed skill explicitly.
Download the boards, model scripts, native reports and edit manifests. The manufacturer's final stackup, plating, isolation environment and physical current/thermal/transient tests remain necessary before production use.
# BMS: revisited copper, 3D X-ray and calculated current density
Kale's original board is on the left; Astra's revised copy is on the right. This review revisits the loss of the 3.3 V plane and the reduced interlayer connections exposed by the previous comparison. It preserves the original and previous Astra board as separate checkpoints. These films are derived native-board analysis graphics and inspection holds, not a recording of fresh live routing.
<video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/10-bms-3d-xray-current-review.mp4"></video>
The narrated review begins at the board file's actual layer spacing, then separates the four layers by 23.6 times for visibility. Inactive copper is 85% transparent; selected copper with a path to a circuit pad is opaque. Muted blue identifies selected-net regions without a pad path. Plated interlayer connections are drawn vertically. Both boards use the same camera, orientation and scale.
## Inspect all 236 nets
<video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/11-bms-3d-xray-all-236-nets.mp4"></video>
This silent 15:44 atlas holds each matched net for four seconds in a stacked X-ray comparison. It contains no current-density overlay. A nominal zone net name is not proof that an orphan island joins that circuit. The narrative film applies current colors only to the two explicitly modeled load cases below.
## What changed
The 3.3 V region on In2.Cu grows from 4.49 mm² in the previous Astra board to 1079.95 mm², compared with 1060.66 mm² on Kale's board. Of the revised inner-layer supply copper, 816.96 mm² has a geometric path to circuit pads and 262.99 mm² is retained but floating. This restores a supply-plane candidate; it also reallocates QGND copper on that layer, so it is not proof of equivalent reference continuity or impedance. Footprints, pad positions and net membership are unchanged.
The revision adds 48 power-path through vias: 24 on the shared drain, 12 on PACK+, and 12 on FBAT. They have 0.6 mm diameter and 0.3 mm drill. Placement was checked against fixed other-net copper, followed by native refill and DRC. A second audit added another 52 supply/reference stitches: one 3.3 V via, 23 VSS, 16 PGND and 12 QGND. This reduced nominal-net copper with no pad path from about 5382 to 2120 mm² in the geometric audit. Existing electrical clearances were not reduced. Via plating and assembly treatment still need manufacturing confirmation.
The user explicitly permits orphaned pours to reduce copper ablation. The revision retains them within the existing clearances and keepouts. Copper assigned to sensitive switching or isolation regions still needs functional review; no floating island receives load-current credit simply because it has a zone net label.
| Board | F.Cu mm² | In1.Cu mm² | In2.Cu mm² | B.Cu mm² | Total mm² |
| --- | ---: | ---: | ---: | ---: | ---: |
| Kale original | 9674.0 | 11295.6 | 9092.6 | 8116.4 | 38178.6 |
| Previous Astra | 8883.7 | 9799.0 | 8875.7 | 8917.9 | 36476.2 |
| Astra revisited | 9569.4 | 10128.6 | 9692.6 | 9671.0 | 39061.6 |
Totals union all refilled conductor geometry, including pads, tracks, vias and assigned graphics, subtract drill voids, and clip to the board. The revised total is 7.09% above the prior Astra candidate and 2.31% above Kale, including retained floating copper. Projected area is not laser time or thermal performance.
## Current density, not temperature
The first-order DC model uses 35 µm copper at 20°C, with the [100% IACS reference resistivity](https://www.copper.org/publications/pub_list/pdf/a1360.pdf), and provisional 25 µm via plating. Copper-center spacing is 0.508186 mm from the board file. Source/sink contacts are ideal equipotential regions. The solver distributes current through planar copper and resistive plated barrels; it does not impose equal current per pin or layer.
- **CD:** 6 A between populated Q8 drain pads 5–9 and Q9 drain pads 5–9. DNP devices receive no source or assumed parallel conduction.
- **PACK+:** 6 A between Q9 source pads 1–3 and the combined front annuli of MC25/MC26. This is a specified comparison boundary condition, not a verified connector assembly or contact-resistance model.
| Calculated copper-only drop at 6 A | Kale | Previous Astra | Revised Astra |
| --- | ---: | ---: | ---: |
| Shared drain, 0.1 mm mesh | 3.54 mV | 3.08 mV | 2.42 mV |
| PACK+, 0.075 mm mesh | 6.05 mV | Not evaluated in this revision | 4.27 mV |
These are provisional coupon-like conductor calculations. They omit solder/contact and package resistance, temperature feedback, switching, inductance and external wiring. They do not establish full pack voltage drop, a current rating, junction temperature or a qualified design.
The paired drain maps share a 0–40 A/mm² scale, with values above 40 saturated red. PACK+ uses 0–80 A/mm², with values above 80 saturated red. Colors show in-plane current density, not barrel current or temperature. Small contacts can concentrate current even when the surrounding pour is broad. The raw corner/contact maxima changed substantially on mesh refinement and are deliberately not promoted as precise physical peak values.
Current and power balance residuals are below 1e-8 relative in the documented solves. A rectangular discrete conductor matches its analytical resistance to better than 1e-8 relative. Halving the drain mesh from 0.2 to 0.1 mm and PACK+ from 0.15 to 0.075 mm changes the compared effective resistances by under 3%. This supports the observed resistance trend, not convergence of local maxima. Varying revised drain via plating from 18 to 35 µm changes its calculated drop from about 2.49 to 2.36 mV. Other fabrication and contact uncertainties remain.
## Native validation, with the actual findings
The retained-island board reports **199 isolated-copper warnings and one zone-to-zone connection error** under the inherited rules. It is not described as a zero-open board. A separate diagnostic copy with island removal enabled reports **zero opens and zero violations**, supporting classification of that retained-board connection report as island-related rather than a lost pad connection.
With ignored keepout, mask and dangling-via checks enabled on preserved comparison copies, Kale reports four keepout findings, 71 mask items and 12 dangling-via warnings. The revision reports four keepout findings, 81 mask items, 199 island warnings and the one zone connection error. All revised mask items identify the existing E1–E6 spark-gap apertures; none identifies a new via or another aperture. The increased item count remains disclosed and those features require assembly/electrical review. No rules were suppressed to improve this result.
Removing islands can let other nets refill the vacated area, so subtracting two refills is not an exact floating-area measurement. The analysis separately classifies conductor components on the actual retained board by paths through plated holes to circuit pads. A path to any pad is different from membership in an active 6 A load case.
## How Adom makes it reproducible
Codex Astra in Adom Hydrogen planned the changes. Adom Bridge's explicit-target `run_script` calls ran native KiCad Python edits, refill, uncapped CLI DRC and exports on ConfRoomROG. `kicad_status` verified the installed test runtime, KiCad Bridge 0.9.347 with KiCad 10.0.5. `pull_file` transferred native evidence back for analysis. The numerical solve and 3D rendering ran separately in the container. No external autorouter was used, and this revision is not presented as live per-trace replay.
General guidance is included in the **adom/codex 0.1.22** package, in `codex-adom-electrical-routing` and its `references/multilayer-current-review.md`, with an ablation-skill cross-reference. It teaches preserved checkpoints, matched net highlights, actual versus exploded layer spacing, explicit electrical boundary conditions, convergence checks, orphan classification, native validation and honest narration. It does not impose this BMS's 6 A load or via assumptions on another board. Install or update the package, then start a fresh Codex session to load its catalog; an existing thread can read the installed skill explicitly.
[Download the boards, model scripts, native reports and edit manifests](https://wiki.adom.inc/api/pages/adom/codex/files/boards/bms-xray-review-evidence.zip). The manufacturer's final stackup, plating, isolation environment and physical current/thermal/transient tests remain necessary before production use.