Codex

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@@ -159,3 +159,12 @@ Try asking Codex: The skills give future users a reusable engineering workflow. Execution still requires an available Codex model, KiCad, a connected Adom Bridge and compatible routing verbs; the per-net KiCad Bridge changes are now released to insiders, with 0.9.347 verified for this BMS replay. Earlier films retain their historical development-build context. The package does not bundle a finished universal autorouter or guarantee a production-ready board. Each design's geometry, electrical limits and manufacturing requirements must be calculated and checked.  This is how the ecosystem carries the work forward: improvements are saved in shared source, released in the package tarball, installed into the user's AI environment, and applied to the next design. See the [electrical-routing guide](https://wiki.adom.inc/adom/codex/files/docs/ELECTRICAL-ROUTING.md) and [bootstrap details](https://wiki.adom.inc/adom/codex/files/docs/BOOTSTRAP.md).+++## 9. Revisited BMS copper in 3D, with calculated current density++<video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/10-bms-3d-xray-current-review.mp4"></video>++The revised BMS restores the 3.3 V inner plane, adds power and reference stitching vias and retains permitted orphan copper for ablation. This comparison shows Kale and Astra side by side with 85% transparent context copper, opaque connected-net highlights, and explicitly bounded 6 A current-density calculations on the shared drain and PACK+ paths. It is derived analysis imagery, not live routing or a temperature measurement.++[Open the detailed review and full 236-net X-ray atlas](https://wiki.adom.inc/adom/codex/files/docs/BMS-XRAY-REVIEW.md), including native findings, numerical assumptions, measured limits and the general skills shipped in the Codex package.

@@ -0,0 +1,71 @@+# BMS: revisited copper, 3D X-ray and calculated current density++Kale's original board is on the left; Astra's revised copy is on the right. This review revisits the loss of the 3.3 V plane and the reduced interlayer connections exposed by the previous comparison. It preserves the original and previous Astra board as separate checkpoints. These films are derived native-board analysis graphics and inspection holds, not a recording of fresh live routing.++<video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/10-bms-3d-xray-current-review.mp4"></video>++The narrated review begins at the board file's actual layer spacing, then separates the four layers by 23.6 times for visibility. Inactive copper is 85% transparent; selected copper with a path to a circuit pad is opaque. Muted blue identifies selected-net regions without a pad path. Plated interlayer connections are drawn vertically. Both boards use the same camera, orientation and scale.++## Inspect all 236 nets++<video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/11-bms-3d-xray-all-236-nets.mp4"></video>++This silent 15:44 atlas holds each matched net for four seconds in a stacked X-ray comparison. It contains no current-density overlay. A nominal zone net name is not proof that an orphan island joins that circuit. The narrative film applies current colors only to the two explicitly modeled load cases below.++## What changed++![Restored supply plane in the layer stack](https://wiki.adom.inc/api/pages/adom/codex/files/screenshots/bms-xray-supply.png)++The 3.3 V region on In2.Cu grows from 4.49 mm² in the previous Astra board to 1079.95 mm², compared with 1060.66 mm² on Kale's board. Of the revised inner-layer supply copper, 816.96 mm² has a geometric path to circuit pads and 262.99 mm² is retained but floating. This restores a supply-plane candidate; it also reallocates QGND copper on that layer, so it is not proof of equivalent reference continuity or impedance. Footprints, pad positions and net membership are unchanged.++The revision adds 48 power-path through vias: 24 on the shared drain, 12 on PACK+, and 12 on FBAT. They have 0.6 mm diameter and 0.3 mm drill. Placement was checked against fixed other-net copper, followed by native refill and DRC. A second audit added another 52 supply/reference stitches: one 3.3 V via, 23 VSS, 16 PGND and 12 QGND. This reduced nominal-net copper with no pad path from about 5382 to 2120 mm² in the geometric audit. Existing electrical clearances were not reduced. Via plating and assembly treatment still need manufacturing confirmation.++The user explicitly permits orphaned pours to reduce copper ablation. The revision retains them within the existing clearances and keepouts. Copper assigned to sensitive switching or isolation regions still needs functional review; no floating island receives load-current credit simply because it has a zone net label.++| Board | F.Cu mm² | In1.Cu mm² | In2.Cu mm² | B.Cu mm² | Total mm² |+| --- | ---: | ---: | ---: | ---: | ---: |+| Kale original | 9674.0 | 11295.6 | 9092.6 | 8116.4 | 38178.6 |+| Previous Astra | 8883.7 | 9799.0 | 8875.7 | 8917.9 | 36476.2 |+| Astra revisited | 9569.4 | 10128.6 | 9692.6 | 9671.0 | 39061.6 |++Totals union all refilled conductor geometry, including pads, tracks, vias and assigned graphics, subtract drill voids, and clip to the board. The revised total is 7.09% above the prior Astra candidate and 2.31% above Kale, including retained floating copper. Projected area is not laser time or thermal performance.++![Copper retention and floating islands](https://wiki.adom.inc/api/pages/adom/codex/files/screenshots/bms-xray-islands.png)++## Current density, not temperature++![Shared drain current-density comparison](https://wiki.adom.inc/api/pages/adom/codex/files/screenshots/bms-xray-current.png)++The first-order DC model uses 35 µm copper at 20°C, with the [100% IACS reference resistivity](https://www.copper.org/publications/pub_list/pdf/a1360.pdf), and provisional 25 µm via plating. Copper-center spacing is 0.508186 mm from the board file. Source/sink contacts are ideal equipotential regions. The solver distributes current through planar copper and resistive plated barrels; it does not impose equal current per pin or layer.++- **CD:** 6 A between populated Q8 drain pads 5–9 and Q9 drain pads 5–9. DNP devices receive no source or assumed parallel conduction.+- **PACK+:** 6 A between Q9 source pads 1–3 and the combined front annuli of MC25/MC26. This is a specified comparison boundary condition, not a verified connector assembly or contact-resistance model.++| Calculated copper-only drop at 6 A | Kale | Previous Astra | Revised Astra |+| --- | ---: | ---: | ---: |+| Shared drain, 0.1 mm mesh | 3.54 mV | 3.08 mV | 2.42 mV |+| PACK+, 0.075 mm mesh | 6.05 mV | Not evaluated in this revision | 4.27 mV |++These are provisional coupon-like conductor calculations. They omit solder/contact and package resistance, temperature feedback, switching, inductance and external wiring. They do not establish full pack voltage drop, a current rating, junction temperature or a qualified design.++![PACK+ concentrations near contacts](https://wiki.adom.inc/api/pages/adom/codex/files/screenshots/bms-xray-pack.png)++The paired drain maps share a 0–40 A/mm² scale, with values above 40 saturated red. PACK+ uses 0–80 A/mm², with values above 80 saturated red. Colors show in-plane current density, not barrel current or temperature. Small contacts can concentrate current even when the surrounding pour is broad. The raw corner/contact maxima changed substantially on mesh refinement and are deliberately not promoted as precise physical peak values.++Current and power balance residuals are below 1e-8 relative in the documented solves. A rectangular discrete conductor matches its analytical resistance to better than 1e-8 relative. Halving the drain mesh from 0.2 to 0.1 mm and PACK+ from 0.15 to 0.075 mm changes the compared effective resistances by under 3%. This supports the observed resistance trend, not convergence of local maxima. Varying revised drain via plating from 18 to 35 µm changes its calculated drop from about 2.49 to 2.36 mV. Other fabrication and contact uncertainties remain.++## Native validation, with the actual findings++The retained-island board reports **199 isolated-copper warnings and one zone-to-zone connection error** under the inherited rules. It is not described as a zero-open board. A separate diagnostic copy with island removal enabled reports **zero opens and zero violations**, supporting classification of that retained-board connection report as island-related rather than a lost pad connection.++With ignored keepout, mask and dangling-via checks enabled on preserved comparison copies, Kale reports four keepout findings, 71 mask items and 12 dangling-via warnings. The revision reports four keepout findings, 81 mask items, 199 island warnings and the one zone connection error. All revised mask items identify the existing E1–E6 spark-gap apertures; none identifies a new via or another aperture. The increased item count remains disclosed and those features require assembly/electrical review. No rules were suppressed to improve this result.++Removing islands can let other nets refill the vacated area, so subtracting two refills is not an exact floating-area measurement. The analysis separately classifies conductor components on the actual retained board by paths through plated holes to circuit pads. A path to any pad is different from membership in an active 6 A load case.++## How Adom makes it reproducible++Codex Astra in Adom Hydrogen planned the changes. Adom Bridge's explicit-target `run_script` calls ran native KiCad Python edits, refill, uncapped CLI DRC and exports on ConfRoomROG. `kicad_status` verified the installed test runtime, KiCad Bridge 0.9.347 with KiCad 10.0.5. `pull_file` transferred native evidence back for analysis. The numerical solve and 3D rendering ran separately in the container. No external autorouter was used, and this revision is not presented as live per-trace replay.++General guidance is included in the **adom/codex 0.1.22** package, in `codex-adom-electrical-routing` and its `references/multilayer-current-review.md`, with an ablation-skill cross-reference. It teaches preserved checkpoints, matched net highlights, actual versus exploded layer spacing, explicit electrical boundary conditions, convergence checks, orphan classification, native validation and honest narration. It does not impose this BMS's 6 A load or via assumptions on another board. Install or update the package, then start a fresh Codex session to load its catalog; an existing thread can read the installed skill explicitly.++[Download the boards, model scripts, native reports and edit manifests](https://wiki.adom.inc/api/pages/adom/codex/files/boards/bms-xray-review-evidence.zip). The manufacturer's final stackup, plating, isolation environment and physical current/thermal/transient tests remain necessary before production use.

@@ -4,7 +4,7 @@   "type": "app",   "title": "Codex",   "brief": "Codex in Adom Hydrogen: ecosystem setup, dock dashboard and live engineering demos.",-  "version": "0.1.21",+  "version": "0.1.22",   "description": "Codex in Adom Hydrogen with reusable CAD routing, electrical review, copper-ablation and narrated video skills, plus verified KiCad and Fusion demo progressions.",   "org": "adom",   "needs_sudo": false,

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@@ -38,3 +38,6 @@ Use codex-adom-routing-video for native recording and narration, and codex-adom- Record genuine CAD changes and retain raw captures. Distinguish precomputed planning from live geometry creation, edited takes from continuous recording, and playback speed from elapsed computation time. Narrate the actual measured result, selected process limit, larger electrical clearances, and remaining engineering work.  For the BQ25792 example and its evolving acceptance evidence, read [references/bq25792.md](references/bq25792.md). Example dimensions and net names are not universal defaults.+++For transparent multilayer comparisons and current-density analysis, read the general [multilayer current review](../codex-adom-electrical-routing/references/multilayer-current-review.md). When islands are permitted, measure retained floating copper separately from connected conductors. Preserve the actual orphan warnings, and use a separate island-removal diagnostic to distinguish intentionally retained copper from lost circuit connectivity. Do not suppress the reports or call the retained-island board zero-open when its native report says otherwise.

@@ -1,6 +1,6 @@ --- name: codex-adom-electrical-routing-description: Route or review a PCB with electrical constraints, power and ground pours, clean signal geometry, and copper-retention goals for subtractive or copper-ablation fabrication. Use before claiming an AI-routed board is electrically ready or recording a production-oriented routing demo.+description: Route or review a PCB with electrical constraints, power and ground pours, clean signal geometry, and copper-retention goals for subtractive or copper-ablation fabrication. Use for multilayer X-ray comparisons, current-density maps, copper choke points, or before claiming an AI-routed board is electrically ready. --- Parent skill: codex-adom @@ -96,3 +96,8 @@ Use identical coordinates, layer orientation and zoom for paired views. Label ex Measure total refilled copper unions on every layer as well as selected net areas. Deduct drill voids and clip to the board outline. Larger selected power pours can coexist with lower whole-board copper retention, lost supply planes, fewer thermal vias or different interlayer current paths. Report those tradeoffs before claiming an improvement against a fabrication objective. Track-primitive length alone is not a meaningful end-to-end routing score when one board carries current through polygons or pours.  Treat comparison findings as review inputs. Do not silently alter the candidate to hide a regression, equate fewer vias with better routing, or infer supply impedance, heat flow, current rating or laser time from projected area. Keep the electrical and physical validation limits visible alongside geometric successes.+++# Multilayer current and X-ray review++For transparent layer stacks, highlighted interlayer copper, current-density maps, choke-point comparisons or retained floating islands, read [references/multilayer-current-review.md](references/multilayer-current-review.md). Use this general workflow across boards and bridges; do not reuse example loads without verification.

@@ -0,0 +1,21 @@+# Multilayer X-ray and current-density reviews++Use native, refilled conductor geometry, including net-assigned graphics, pads, tracks, vias and pours. Preserve original and successive candidate boards with hashes and validation evidence. Compare matched nets by pad membership using a common camera, scale and layer orientation. A translucent exported 3D stack is an analysis visualization, not native editor footage.++Show inactive copper at the requested opacity and the selected net opaque across all layers. Distinguish opacity from transparency. Keep layer names and order visible. Read dielectric spacing and copper thickness from the board, and distinguish design-file values from confirmed fabrication specifications. Label any exploded or vertically exaggerated stack, with a true-scale option. Render holes and actual plated interlayer connections; do not draw an electrical connection merely because shapes overlap in projection.++A current-density overlay needs a stated load case and source/sink terminals. Verify populated versus DNP parts, parallel paths, separate grounds, net ties, shunts and Kelvin sense connections. Do not assume every connector carries full load or distribute current equally among layers or device pads without a model that justifies it. Leave unknown-load nets uncolored or present a separately labeled normalized unit-current calculation.++For a coupled-layer DC model, record copper conductivity and temperature, thickness, via drill and plating, layer spacing, terminal boundary conditions, mesh construction and treatment of holes. Unknown via plating requires an explicit provisional assumption and sensitivity analysis. Avoid raster shortcuts across isolation gaps and account for narrow partial cells or refine the mesh. Validate current conservation, power balance and a known rectangular conductor; check convergence for resistance and reported neck metrics. Singular contact/corner peaks and unresolved necks must not be presented as precise physical maxima.++Use consistent units, legends and color limits for matched comparisons. Current density, potential drop and resistive loss are different quantities. None is a measured temperature map or a current rating. State omitted contact/package resistance, switching/transient effects and thermal feedback. Preserve the numerical data and model inputs with the video.++Use findings to revisit supply-plane coverage, return continuity, necks and interlayer connections. More copper on selected nets or fewer vias is not automatically better. Report total conductor retention and displaced reference copper too. Refill and run uncapped native DRC on every accepted revision, compare stricter diagnostic results against the preserved original, and record unresolved electrical qualification limits. Keep example-specific loads and host paths out of the general skill.++When the user explicitly permits orphaned pours for copper ablation, preserve permissible floating islands rather than automatically deleting them. Keep clearance and isolation barriers intact. Report connected copper and floating retention separately. A zone net label does not establish a conducting path: disconnected islands must not carry modeled load current or be presented as connected thermal spreading. Visually distinguish floating islands in net highlights, and omit them from the electrical solve or solve them as unexcited floating conductors without inventing sources.++Do not assume subtracting an island-removed refill from an island-retaining refill gives the exact floating area. Removing a high-priority island can let another net refill the vacated space, changing both sides of the geometric difference. Classify connected components on the actual retained board using native connectivity or an explicitly checked conductor graph through plated holes. State whether connected means a path to any circuit pad or to the active source/sink network; those are different criteria.++After enabling orphan retention, audit supply and reference planes again. A large nominal supply region can be half floating and displace useful connected ground. Prefer connecting useful regions with clearance-checked stitching where a same-net path exists on another layer. Retain the remaining permissible islands for fabrication only. Refill, reclassify and validate after stitching; update the numerical input hash and rendered geometry together. Do not reuse a prior iteration's attractive video or current map on an altered board without proving the modeled conductor geometry is unchanged.++Discover the selected bridge's current export, net-highlight and 3D-view capabilities before choosing a renderer. If the native viewer does not provide the requested opacity or field overlay, use native exported geometry for a separate, labeled analysis artifact. Do not invent a bridge verb or imply that postprocessed X-ray imagery is a native CAD viewer feature. Preserve which work ran through the bridge and which ran in the separate solver or renderer.

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