# CM4407

**Applied Power** · MOSFETs · SO-8

CM4407 from Applied Power, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied with pins 2 and 3; drain-source voltage rated -30V. |
| 2 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 3; continuous drain current rated -12.3A at TA=25°C. |
| 3 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 2; body-diode continuous current is -12.3A. |
| 4 | G | input | Gate of the P-channel MOSFET; gate-source voltage is limited to ±25V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied with pins 6, 7 and 8; VDS is -30V maximum. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 7 and 8; pulsed drain current is -48.2A maximum. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 8; RDS(on) is below 12.5mΩ at VGS=-10V. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 7; RDS(on) is below 25mΩ at VGS=-4.5V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Applied Power |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source Voltage | VDS |  |  | -30 | V |  | 1 |
| Gate-source Voltage | VGS | -25 |  | 25 | V |  | 1 |
| Continuous Drain Current | ID |  |  | -12.3 | A | TA=25°C | 1 |
| Continuous Drain Current | ID |  |  | -10.8 | A | TA=70°C | 1 |
| Pulsed Drain Current | IDM |  |  | -48.2 | A | Pulse test note (1) | 1 |
| Total Power Dissipation | PD |  |  | 2.5 | W | TA=25°C (note 2) | 1 |
| Thermal Resistance Junction-to-Ambient | RθJA |  |  | 50 | °C/W | Note (2) | 1 |
| Junction and Storage Temperature Range | TJ,TSTG | -55 |  | 150 | °C |  | 1 |
| Drain-Source Breakdown Voltage | BVDSS | -30 |  |  | V | VGS=0V,ID=-250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | μA | VDS=- 30V,VGS=0V,TC=25°C | 2 |
| Gate-Body Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±25V,VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 |  | -3 | V | VDS=VGS,ID=-250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 9 | 11 | mΩ | VGS=-20V,ID=-12A | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 10.2 | 12.5 | mΩ | VGS=-10V,ID=-12A | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 16 | 25 | mΩ | VGS=-4.5V,ID=-10A | 2 |
| Diode Forward Voltage | VSD |  | -0.8 | -1.2 | V | IS=-12.3A,VGS=0V | 2 |
| Maximum Body-Diode Continuous Current | IS |  |  | -12.3 | A |  | 2 |

## CAD (KiCad official)

- Symbol: `CM4407`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `cm4407-etched.step` / `cm4407-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cm4407.step` / `cm4407.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Applied Power datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590466777663496192) (5 pp, sha256 `a467130bd29818b5`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cm4407-datasheet.pdf)