component
CM1348-QFNTR
Public Made by Adomby adom
CIMO Analog To Digital Converters (ADC), QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "cm1348-qfntr",
"version": "0.1.0",
"type": "component",
"description": "CIMO Analog To Digital Converters (ADC), QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"data acquisition",
"cm1348-qfntr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cm1348-qfntr.kicad_sym",
"cm1348-qfntr.kicad_mod",
"cm1348-qfntr.glb",
"cm1348-qfntr.step",
"cm1348-qfntr.lbr",
"docs/hero.png",
"docs/cm1348-qfntr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cm1348-qfntr-hero.glb",
"cm1348-qfntr-hero.overlay.json",
"cm1348-qfntr-etched.glb"
],
"component": {
"mpn": "CM1348-QFNTR",
"manufacturer": "CIMO",
"package": "QFN-48(7x7)",
"pin_count": 49,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8618864913075232768",
"parts": {
"symbol": "cm1348-qfntr.kicad_sym",
"footprint": "cm1348-qfntr.kicad_mod",
"model_3d": "cm1348-qfntr-hero.glb",
"model_3d_plain": "cm1348-qfntr-etched.glb",
"model_3d_step": "cm1348-qfntr-etched.step",
"model_3d_step_plain": "cm1348-qfntr.step",
"lbr": "cm1348-qfntr.lbr"
},
"distributor_links": {
"lcsc": "C22446833"
},
"distributor_check": {
"checked_at": "2026-10-21T00:09:04Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "AIN3",
"type": "input",
"description": "Single-ended analog input channel 3 and differential input channel 1 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "2",
"name": "AIN2",
"type": "input",
"description": "Single-ended analog input channel 2 and differential input channel 1 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "3",
"name": "AIN1",
"type": "input",
"description": "Single-ended analog input channel 1 and differential input channel 0 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "4",
"name": "AIN0",
"type": "input",
"description": "Single-ended analog input channel 0 and differential input channel 0 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "5",
"name": "AVSS",
"type": "power_in",
"description": "Analog negative supply: 0 V for unipolar operation or −2.5 V for bipolar operation, with AVSS specified from −2.6 V to 0 V."
},
{
"number": "6",
"name": "AVDD",
"type": "power_in",
"description": "Analog positive supply: 5 V for unipolar operation or +2.5 V for bipolar operation; AVDD−AVSS is specified from 4.75 V to 5.25 V."
},
{
"number": "7",
"name": "PLLCAP",
"type": "passive",
"description": "PLL bypass capacitor pin; connect a 22 nF capacitor to AVSS when the crystal oscillator is used."
},
{
"number": "8",
"name": "XTAL1",
"type": "passive",
"description": "32.768 kHz crystal oscillator input pin 1, which must not be connected to any other circuit."
},
{
"number": "9",
"name": "XTAL2",
"type": "passive",
"description": "32.768 kHz crystal oscillator input pin 2, which must not be connected to any other circuit."
},
{
"number": "10",
"name": "PWDN",
"type": "input",
"description": "Power-down control; holding the pin low for more than 2 fCLK cycles enters low-power mode."
},
{
"number": "11",
"name": "RESET",
"type": "input",
"description": "Reset input; holding the pin low for more than 2 fCLK cycles resets the chip."
},
{
"number": "12",
"name": "CLKSEL",
"type": "input",
"description": "Clock select: low selects the crystal oscillator with fCLK output on CLKIO, high disables the crystal and feeds an external clock into CLKIO."
},
{
"number": "13",
"name": "CLKIO",
"type": "bidirectional",
"description": "System clock input or output depending on CLKSEL; external clock input range is 0.1 MHz to 16 MHz with 40% to 60% duty cycle."
},
{
"number": "14",
"name": "GPIO0",
"type": "bidirectional",
"description": "General-purpose digital input/output 0; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "15",
"name": "GPIO1",
"type": "bidirectional",
"description": "General-purpose digital input/output 1; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "16",
"name": "GPIO2",
"type": "bidirectional",
"description": "General-purpose digital input/output 2; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "17",
"name": "GPIO3",
"type": "bidirectional",
"description": "General-purpose digital input/output 3; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "18",
"name": "GPIO4",
"type": "bidirectional",
"description": "General-purpose digital input/output 4; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "19",
"name": "GPIO5",
"type": "bidirectional",
"description": "General-purpose digital input/output 5; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "20",
"name": "GPIO6",
"type": "bidirectional",
"description": "General-purpose digital input/output 6; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "21",
"name": "GPIO7",
"type": "bidirectional",
"description": "General-purpose digital input/output 7; pins default to input after power-on or reset and must not be left floating."
},
{
"number": "22",
"name": "SCLK",
"type": "input",
"description": "SPI interface clock input; data is latched on the rising edge and output on the falling edge."
},
{
"number": "23",
"name": "DIN",
"type": "input",
"description": "SPI interface data input."
},
{
"number": "24",
"name": "DOUT",
"type": "output",
"description": "SPI interface data output, which is tri-stated when CS is deasserted high."
},
{
"number": "25",
"name": "DRDY",
"type": "output",
"description": "Data-ready output, active low."
},
{
"number": "26",
"name": "START",
"type": "input",
"description": "Start-conversion input, active high; continuous conversion requires it held high."
},
{
"number": "27",
"name": "CS",
"type": "input",
"description": "SPI interface chip select input, active low."
},
{
"number": "28",
"name": "DVDD",
"type": "power_in",
"description": "Digital supply pin, specified at 2.7 V to 5.5 V in the pin table (2.7 V to 5.25 V in the electrical specification)."
},
{
"number": "29",
"name": "DGND",
"type": "power_in",
"description": "Digital ground."
},
{
"number": "30",
"name": "VREFN",
"type": "input",
"description": "Negative reference input; allowed range is AVSS−0.1 V to VREFP−1.2 V."
},
{
"number": "31",
"name": "VREFP",
"type": "input",
"description": "Positive reference input; allowed range is 4.096 V to AVDD, and VREF = VREFP−VREFN must be at least 4.096 V."
},
{
"number": "32",
"name": "AINCOM",
"type": "input",
"description": "Common reference ground for all single-ended inputs, which can be set within ±100 mV of the analog supply range."
},
{
"number": "33",
"name": "AIN15",
"type": "input",
"description": "Single-ended analog input channel 15 and differential input channel 7 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "34",
"name": "AIN14",
"type": "input",
"description": "Single-ended analog input channel 14 and differential input channel 7 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "35",
"name": "AIN13",
"type": "input",
"description": "Single-ended analog input channel 13 and differential input channel 6 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "36",
"name": "AIN12",
"type": "input",
"description": "Single-ended analog input channel 12 and differential input channel 6 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "37",
"name": "AIN11",
"type": "input",
"description": "Single-ended analog input channel 11 and differential input channel 5 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "38",
"name": "AIN10",
"type": "input",
"description": "Single-ended analog input channel 10 and differential input channel 5 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "39",
"name": "AIN9",
"type": "input",
"description": "Single-ended analog input channel 9 and differential input channel 4 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "40",
"name": "AIN8",
"type": "input",
"description": "Single-ended analog input channel 8 and differential input channel 4 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "41",
"name": "ADCINN",
"type": "input",
"description": "ADC differential input (−), which receives the externally conditioned signal when BYPAS = 1; ADC input is measured as VIN = ADCINP−ADCINN."
},
{
"number": "42",
"name": "ADCINP",
"type": "input",
"description": "ADC differential input (+), which receives the externally conditioned signal when BYPAS = 1; ADC input is measured as VIN = ADCINP−ADCINN."
},
{
"number": "43",
"name": "MUXOUTN",
"type": "output",
"description": "Multiplexer differential output (−) used to route the selected channel off-chip for external signal conditioning."
},
{
"number": "44",
"name": "MUXOUTP",
"type": "output",
"description": "Multiplexer differential output (+) used to route the selected channel off-chip for external signal conditioning."
},
{
"number": "45",
"name": "AIN7",
"type": "input",
"description": "Single-ended analog input channel 7 and differential input channel 3 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "46",
"name": "AIN6",
"type": "input",
"description": "Single-ended analog input channel 6 and differential input channel 3 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "47",
"name": "AIN5",
"type": "input",
"description": "Single-ended analog input channel 5 and differential input channel 2 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "48",
"name": "AIN4",
"type": "input",
"description": "Single-ended analog input channel 4 and differential input channel 2 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND."
},
{
"number": "49",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet lists an exposed pad (EPAD) typed NC with no electrical connection, which is not a num; Analog-input and reference pins (AI) are mapped to KiCad 'input' and analog outputs (AO) to 'output'; DOUT is typed DO in the datasheet and mapped to 'output', but the datasheet states it is tri-stated ",
"2/49 pins cited to the wrong page (name found elsewhere): ['8:XTAL1@p5', '9:XTAL2@p5']"
],
"pages_sent": 37,
"cost_usd": 0.17,
"at": "2026-10-21T00:05:17"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8618864913075232768",
"pages": 37,
"sha256": "a7ce7763f2144ffe",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cm1348-qfntr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.0,
7.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
"checked": "2026-10-21",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cm1348-qfntr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.0,
7.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "eedfa6d59a6d705f1bb81b1382a4728e6eb103cbcec3b442d67eddb8b7db65c7",
"checked": "2026-10-21",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}