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CM1348-QFNTR

CIMO · Analog To Digital Converters (ADC) · QFN-48(7x7)

CM1348-QFNTR from CIMO, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AIN3	input	Single-ended analog input channel 3 and differential input channel 1 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
2	AIN2	input	Single-ended analog input channel 2 and differential input channel 1 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
3	AIN1	input	Single-ended analog input channel 1 and differential input channel 0 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
4	AIN0	input	Single-ended analog input channel 0 and differential input channel 0 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
5	AVSS	power_in	Analog negative supply: 0 V for unipolar operation or −2.5 V for bipolar operation, with AVSS specified from −2.6 V to 0 V.
6	AVDD	power_in	Analog positive supply: 5 V for unipolar operation or +2.5 V for bipolar operation; AVDD−AVSS is specified from 4.75 V to 5.25 V.
7	PLLCAP	passive	PLL bypass capacitor pin; connect a 22 nF capacitor to AVSS when the crystal oscillator is used.
8	XTAL1	passive	32.768 kHz crystal oscillator input pin 1, which must not be connected to any other circuit.
9	XTAL2	passive	32.768 kHz crystal oscillator input pin 2, which must not be connected to any other circuit.
10	PWDN	input	Power-down control; holding the pin low for more than 2 fCLK cycles enters low-power mode.
11	RESET	input	Reset input; holding the pin low for more than 2 fCLK cycles resets the chip.
12	CLKSEL	input	Clock select: low selects the crystal oscillator with fCLK output on CLKIO, high disables the crystal and feeds an external clock into CLKIO.
13	CLKIO	bidirectional	System clock input or output depending on CLKSEL; external clock input range is 0.1 MHz to 16 MHz with 40% to 60% duty cycle.
14	GPIO0	bidirectional	General-purpose digital input/output 0; pins default to input after power-on or reset and must not be left floating.
15	GPIO1	bidirectional	General-purpose digital input/output 1; pins default to input after power-on or reset and must not be left floating.
16	GPIO2	bidirectional	General-purpose digital input/output 2; pins default to input after power-on or reset and must not be left floating.
17	GPIO3	bidirectional	General-purpose digital input/output 3; pins default to input after power-on or reset and must not be left floating.
18	GPIO4	bidirectional	General-purpose digital input/output 4; pins default to input after power-on or reset and must not be left floating.
19	GPIO5	bidirectional	General-purpose digital input/output 5; pins default to input after power-on or reset and must not be left floating.
20	GPIO6	bidirectional	General-purpose digital input/output 6; pins default to input after power-on or reset and must not be left floating.
21	GPIO7	bidirectional	General-purpose digital input/output 7; pins default to input after power-on or reset and must not be left floating.
22	SCLK	input	SPI interface clock input; data is latched on the rising edge and output on the falling edge.
23	DIN	input	SPI interface data input.
24	DOUT	output	SPI interface data output, which is tri-stated when CS is deasserted high.
25	DRDY	output	Data-ready output, active low.
26	START	input	Start-conversion input, active high; continuous conversion requires it held high.
27	CS	input	SPI interface chip select input, active low.
28	DVDD	power_in	Digital supply pin, specified at 2.7 V to 5.5 V in the pin table (2.7 V to 5.25 V in the electrical specification).
29	DGND	power_in	Digital ground.
30	VREFN	input	Negative reference input; allowed range is AVSS−0.1 V to VREFP−1.2 V.
31	VREFP	input	Positive reference input; allowed range is 4.096 V to AVDD, and VREF = VREFP−VREFN must be at least 4.096 V.
32	AINCOM	input	Common reference ground for all single-ended inputs, which can be set within ±100 mV of the analog supply range.
33	AIN15	input	Single-ended analog input channel 15 and differential input channel 7 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
34	AIN14	input	Single-ended analog input channel 14 and differential input channel 7 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
35	AIN13	input	Single-ended analog input channel 13 and differential input channel 6 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
36	AIN12	input	Single-ended analog input channel 12 and differential input channel 6 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
37	AIN11	input	Single-ended analog input channel 11 and differential input channel 5 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
38	AIN10	input	Single-ended analog input channel 10 and differential input channel 5 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
39	AIN9	input	Single-ended analog input channel 9 and differential input channel 4 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
40	AIN8	input	Single-ended analog input channel 8 and differential input channel 4 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
41	ADCINN	input	ADC differential input (−), which receives the externally conditioned signal when BYPAS = 1; ADC input is measured as VIN = ADCINP−ADCINN.
42	ADCINP	input	ADC differential input (+), which receives the externally conditioned signal when BYPAS = 1; ADC input is measured as VIN = ADCINP−ADCINN.
43	MUXOUTN	output	Multiplexer differential output (−) used to route the selected channel off-chip for external signal conditioning.
44	MUXOUTP	output	Multiplexer differential output (+) used to route the selected channel off-chip for external signal conditioning.
45	AIN7	input	Single-ended analog input channel 7 and differential input channel 3 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
46	AIN6	input	Single-ended analog input channel 6 and differential input channel 3 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
47	AIN5	input	Single-ended analog input channel 5 and differential input channel 2 (−); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
48	AIN4	input	Single-ended analog input channel 4 and differential input channel 2 (+); absolute voltage range is AVSS−0.1 V to AVDD+0.1 V relative to DGND.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	CIMO
Package	QFN-48(7x7)
Category	Data Acquisition
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating temperature		-40		125	°C		7
Storage temperature		-60		150	°C		7
Junction temperature				150	°C		7
AVDD to AVSS		-0.3		5.5	V		7
AVSS to DGND		-2.8		0.3	V		7
DVDD to DGND		-0.3		5.5	V		7
Digital input to DGND		-0.3			V	upper limit printed as DVDD+0.3	7
ESD HBM, all pins except analog inputs				2000	V	HBM, all pins except analog inputs	7
ESD HBM, analog input pins only				8000	V	HBM, analog input pins only	7
ESD CDM				1000	V	CDM	7
DVDD digital supply voltage	DVDD	2.7		5.25	V		9
AVSS analog negative supply	AVSS	-2.6		0	V		9
Input clock frequency		0.1		16	MHz		9
Input clock duty cycle		40		60	%		9
Output data rate, auto-scan mode		1.859		29.52	kSPS	自动扫描模式 (auto-scan mode)	8
Integral nonlinearity (INL)	INL		0.0003	0.001	% of FSR	差分输入 (differential input)	8
Offset error, chop enabled			1	10	μV	输入短接，启用斩波 (CHOP = 1)	8
Offset drift, chop enabled			0.02	0.1	μV/°C	启用斩波 (chop enabled)	8
Gain error			0.1	0.3	%		8
Gain drift			0.4	2	ppm/°C		8
Common-mode rejection ratio (CMRR)	CMRR	90	105		dB	fCM = 50Hz/60Hz	8
Power supply rejection ratio, AVDD/AVSS	PSRR	80	95		dB	AVDD，AVSS，fPS = 50Hz/60Hz	8
Power supply rejection ratio, DVDD	PSRR	90	100		dB	DVDD，fPS = 50Hz/60Hz	8
Differential reference input range	VREF	4.096			V	VREF = VREFP - VREFN; upper limit printed as AVDD - AVSS	8
VREFP reference input	VREFP	4.096			V	upper limit printed as AVDD	8
External reference voltage reading error			1	3	%		9
Supply voltage reading error			1	3	%		9
DVDD current, external clock operation	IDVDD		0.15	0.47	mA	外部时钟工作 (external clock)	9
AVDD/AVSS current, conversion mode			4.1	5.1	mA	转换模式 (conversion mode)	9
Digital supply range, electrical table	DVDD	2.7		5.25	V	电源输入 table	9
SCLK high or low pulse width	tSPW	0.8		4096	1/fCLK	SCLK 高电平或低电平脉冲宽度 (SPI reset value max)	10

CAD (KiCad official)

Symbol: CM1348-QFNTR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: QFN-48(7x7) (KiCad packages3D, STEP)
3D model files: cm1348-qfntr-etched.step / cm1348-qfntr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm1348-qfntr.step / cm1348-qfntr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CIMO datasheet (37 pp, sha256 a7ce7763f2144ffe, retrieved 2026-10-21, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF