component

CLVC1G374QDCKRQ1

Public Made by Adom

by adom

Texas Instruments Flip Flops, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs clvc1g374qdckrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers clvc1g374qdckrq1: viewers · Ray
clvc1g374qdckrq1-etched.fit.json clvc1g374qdckrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
clvc1g374qdckrq1-etched.glb clvc1g374qdckrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
clvc1g374qdckrq1-etched.step clvc1g374qdckrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
clvc1g374qdckrq1.glb Publish 0.1.0 · Ray
clvc1g374qdckrq1.kicad_mod Publish 0.1.0 · Ray
clvc1g374qdckrq1.kicad_sym Publish 0.1.0 · Ray
clvc1g374qdckrq1.lbr Publish 0.1.0 · Ray
clvc1g374qdckrq1.step Publish 0.1.0 · Ray
package.json clvc1g374qdckrq1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json clvc1g374qdckrq1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/clvc1g374qdckrq1 · Ray

CLVC1G374QDCKRQ1

Texas Instruments · Flip Flops · SC-70-6

CLVC1G374QDCKRQ1 from Texas Instruments, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; OE low allows Q to output normal logic levels, OE high forces Q to the high-impedance (3-state) state without affecting internal flip-flop operation.
2 VCC power_in Supply voltage pin; recommended operating range is 1.65 V to 5.5 V (1.5 V minimum for data retention only).
3 Q tri_state 3-state data output that is set to the logic level present at D on the positive-going transition of CLK, and goes to high impedance when OE is high.
4 D input Data input whose logic level is transferred to Q on the low-to-high transition of CLK; accepts input voltages up to 5.5 V.
5 GND power_in Ground reference pin for the device.
6 CLK input Clock input; on the positive (low-to-high) transition of CLK, the D input logic level is latched to the Q output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6
Category Logic
Pins 6

CAD (KiCad official)

  • Symbol: CLVC1G374QDCKRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6 (KiCad packages3D, STEP)
  • 3D model files: clvc1g374qdckrq1-etched.step / clvc1g374qdckrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clvc1g374qdckrq1.step / clvc1g374qdckrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 e192d0818c572b44, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF