component
CLVC1G374QDCKRQ1
Public Made by Adomby adom
Texas Instruments Flip Flops, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+42@@ -0,0 +1,42 @@+# CLVC1G374QDCKRQ1++**Texas Instruments** · Flip Flops · SC-70-6++CLVC1G374QDCKRQ1 from Texas Instruments, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered output-enable input; OE low allows Q to output normal logic levels, OE high forces Q to the high-impedance (3-state) state without affecting internal flip-flop operation. |+| 2 | VCC | power_in | Supply voltage pin; recommended operating range is 1.65 V to 5.5 V (1.5 V minimum for data retention only). |+| 3 | Q | tri_state | 3-state data output that is set to the logic level present at D on the positive-going transition of CLK, and goes to high impedance when OE is high. |+| 4 | D | input | Data input whose logic level is transferred to Q on the low-to-high transition of CLK; accepts input voltages up to 5.5 V. |+| 5 | GND | power_in | Ground reference pin for the device. |+| 6 | CLK | input | Clock input; on the positive (low-to-high) transition of CLK, the D input logic level is latched to the Q output. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SC-70-6 |+| Category | Logic |+| Pins | 6 |++## CAD (KiCad official)++- Symbol: `CLVC1G374QDCKRQ1`+- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`+- 3D model: SC-70-6 (KiCad packages3D, STEP)+- 3D model files: `clvc1g374qdckrq1-etched.step` / `clvc1g374qdckrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `clvc1g374qdckrq1.step` / `clvc1g374qdckrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc1g374-q1) (18 pp, sha256 `e192d0818c572b44`, retrieved 2026-09-24, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/clvc1g374qdckrq1-datasheet.pdf)
page.jsonadded+129@@ -0,0 +1,129 @@+{+ "slug": "clvc1g374qdckrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "clvc1g374qdckrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "clvc1g374qdckrq1.kicad_sym",+ "clvc1g374qdckrq1.kicad_mod",+ "clvc1g374qdckrq1.glb",+ "clvc1g374qdckrq1.step",+ "clvc1g374qdckrq1.lbr",+ "docs/hero.png",+ "docs/clvc1g374qdckrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CLVC1G374QDCKRQ1",+ "manufacturer": "Texas Instruments",+ "package": "SC-70-6",+ "pin_count": 6,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc1g374-q1",+ "parts": {+ "symbol": "clvc1g374qdckrq1.kicad_sym",+ "footprint": "clvc1g374qdckrq1.kicad_mod",+ "model_3d": "clvc1g374qdckrq1-etched.glb",+ "model_3d_plain": "clvc1g374qdckrq1.glb",+ "model_3d_step": "clvc1g374qdckrq1-etched.step",+ "model_3d_step_plain": "clvc1g374qdckrq1.step",+ "lbr": "clvc1g374qdckrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677712"+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Buffered output-enable input; OE low allows Q to output normal logic levels, OE high forces Q to the high-impedance (3-state) state without affecting internal flip-flop operation."+ },+ {+ "number": "2",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage pin; recommended operating range is 1.65 V to 5.5 V (1.5 V minimum for data retention only)."+ },+ {+ "number": "3",+ "name": "Q",+ "type": "tri_state",+ "description": "3-state data output that is set to the logic level present at D on the positive-going transition of CLK, and goes to high impedance when OE is high."+ },+ {+ "number": "4",+ "name": "D",+ "type": "input",+ "description": "Data input whose logic level is transferred to Q on the low-to-high transition of CLK; accepts input voltages up to 5.5 V."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin for the device."+ },+ {+ "number": "6",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; on the positive (low-to-high) transition of CLK, the D input logic level is latched to the Q output."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 18,+ "cost_usd": 0.2389,+ "at": "2026-09-24T03:48:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc1g374-q1",+ "pages": 18,+ "sha256": "e192d0818c572b44",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 6,+ "described": 6,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}