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CLM2543CDW

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CHIPLON Analog To Digital Converters (ADCs), SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CLM2543CDW

CHIPLON · Analog To Digital Converters (ADCs) · SOIC-20

CLM2543CDW from CHIPLON, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN0 input Analog input 0, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
2 AIN1 input Analog input 1, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
3 AIN2 input Analog input 2, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
4 AIN3 input Analog input 3, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
5 AIN4 input Analog input 4, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
6 AIN5 input Analog input 5, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
7 AIN6 input Analog input 6, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
8 AIN7 input Analog input 7, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
9 AIN8 input Analog input 8, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
10 GND power_in Ground return terminal for the internal circuitry; all voltage measurements are referenced to GND unless otherwise noted.
11 AIN9 input Analog input 9, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
12 AIN10 input Analog input 10, multiplexed internally; for 4.1 MHz I/O CLOCK operation drive source impedance should be ≤50 Ω and able to charge 60 pF.
13 REF- input Negative reference voltage, the lower reference value (normally ground); input range is set by the difference between REF+ and REF-.
14 REF+ input Positive reference voltage, the upper reference value (normally VCC); maximum input range is set by the difference between REF+ and REF-.
15 CS input Chip select; a high-to-low transition resets the internal counter and controls and enables DATA OUT, DATA INPUT and I/O CLOCK, while low-to-high disables DATA INPUT and I/O CLOCK within the setup time.
16 DATA OUT tri_state Three-state serial output of the A/D conversion result, high-impedance when CS is high and driven with the previous result's MSB/LSB when CS is low, with subsequent bits shifted out on I/O CLOCK falling edges.
17 DATA INPUT input Serial data input; a 4-bit serial address, MSB first and shifted in on the first four rising edges of I/O CLOCK, selects the analog input or test voltage before conversion.
18 I/O CLOCK input Input/output clock, 0 to 4.1 MHz, that shifts the 8 input data bits in on rising edges, shifts conversion data out of DATA OUT on falling edges, and hands conversion control to the internal state controller on the last falling edge.
19 EOC output End-of-conversion output that goes low after the last I/O CLOCK falling edge and stays low until the conversion is complete and data is ready for transfer.
20 VCC power_in Positive supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 6.5 V).

Key specifications

Parameter Value
Manufacturer CHIPLON
Package SOIC-20
Category ADC/DAC/Data Conversion
Pins 20

CAD (KiCad official)

  • Symbol: CLM2543CDW
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: clm2543cdw-etched.step / clm2543cdw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clm2543cdw.step / clm2543cdw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPLON datasheet (36 pp, sha256 c4eaa1a29bcf6331, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF