CLC001AJE

{
  "slug": "clc001aje",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "clc001aje",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "clc001aje.kicad_sym",
    "clc001aje.kicad_mod",
    "clc001aje.glb",
    "clc001aje.step",
    "clc001aje.lbr",
    "docs/hero.png",
    "docs/clc001aje-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "clc001aje-hero.glb",
    "clc001aje-hero.overlay.json",
    "clc001aje-etched.glb"
  ],
  "component": {
    "mpn": "CLC001AJE",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Interface",
    "subcategory": "LVDS ICs",
    "datasheet": "https://www.ti.com/lit/ds/symlink/clc001.pdf",
    "parts": {
      "symbol": "clc001aje.kicad_sym",
      "footprint": "clc001aje.kicad_mod",
      "model_3d": "clc001aje-hero.glb",
      "model_3d_plain": "clc001aje-etched.glb",
      "model_3d_step": "clc001aje-etched.step",
      "model_3d_step_plain": "clc001aje.step",
      "lbr": "clc001aje.lbr"
    },
    "distributor_links": {
      "lcsc": "C1544145",
      "digikey": "2156-CLC001AJE-ND",
      "mouser": "926-CLC001AJE"
    },
    "distributor_check": {
      "checked_at": "2026-11-05T21:13:55Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "2156-CLC001AJE-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "926-CLC001AJE",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VBB",
        "type": "passive",
        "description": "Optional bias voltage output for the inputs, set by the RBB resistor between 1.3 kΩ and 11.5 kΩ, and left as no connect if unused."
      },
      {
        "number": "2",
        "name": "VIN+",
        "type": "power_in",
        "description": "Positive differential input, accepting LVDS, LVPECL, or attenuated PECL levels."
      },
      {
        "number": "3",
        "name": "VIN-",
        "type": "power_in",
        "description": "Negative differential input, accepting LVDS, LVPECL, or attenuated PECL levels."
      },
      {
        "number": "4",
        "name": "RREF",
        "type": "passive",
        "description": "Output driver level control; a resistor to ground sets the output swing, 1.91 kΩ ±1% for 800 mVp-p or 1.5 kΩ ±1% for 1.0 Vp-p."
      },
      {
        "number": "5",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative power supply, the 0 V reference for all voltages on the device."
      },
      {
        "number": "6",
        "name": "SDO",
        "type": "output",
        "description": "Serial data true output, driving a 75Ω AC-coupled back-matched cable with 800 mVp-p to 1.0 Vp-p swing."
      },
      {
        "number": "7",
        "name": "SDO",
        "type": "output",
        "description": "Serial data complement output, driving a 75Ω AC-coupled back-matched cable paired with the true output."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive power supply, specified from +3.0 V to +3.6 V (3.3 V nominal)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet text gives the complementary output name on pin 7 as 'SDO' without the overbar, which "
        ],
        "pages_sent": 18,
        "cost_usd": 0.0152,
        "at": "2026-11-05T21:13:45"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/clc001.pdf",
        "pages": 18,
        "sha256": "9c4861571890b12a",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "clc001aje.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "clc001aje-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "a9aff01438a8214030e83698af3cea6de1e802e5406414a4f07aa25cec9f6e19",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}