component

CLC001AJE

Public Made by Adom

by adom

Texas Instruments LVDS ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceclc001ajefactory-2.0.0extractor-text

Verified CLC001AJE

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CLC001AJE · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C1544145, digikey 2156-CLC001AJE-ND, mouser 926-CLC001AJE
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1z8u5kx2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ clc001aje.kicad_sym✓ clc001aje.kicad_mod✓ clc001aje.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers clc001aje: viewers · Ray
clc001aje-etched.glb Publish 0.1.0 · Ray
clc001aje-etched.step clc001aje: factory component page (tier=mfr) · Ray
clc001aje-hero.glb clc001aje: hero GLB from the etched model (keeps the MPN mark) · Ray
clc001aje-hero.overlay.json Publish 0.1.0 · Ray
clc001aje.glb Publish 0.1.0 · Ray
clc001aje.kicad_mod Publish 0.1.0 · Ray
clc001aje.kicad_sym Publish 0.1.0 · Ray
clc001aje.lbr Publish 0.1.0 · Ray
clc001aje.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray

CLC001AJE

Texas Instruments · LVDS ICs · SOIC-8

CLC001AJE from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBB passive Optional bias voltage output for the inputs, set by the RBB resistor between 1.3 kΩ and 11.5 kΩ, and left as no connect if unused.
2 VIN+ power_in Positive differential input, accepting LVDS, LVPECL, or attenuated PECL levels.
3 VIN- power_in Negative differential input, accepting LVDS, LVPECL, or attenuated PECL levels.
4 RREF passive Output driver level control; a resistor to ground sets the output swing, 1.91 kΩ ±1% for 800 mVp-p or 1.5 kΩ ±1% for 1.0 Vp-p.
5 VSS power_in Negative power supply, the 0 V reference for all voltages on the device.
6 SDO output Serial data true output, driving a 75Ω AC-coupled back-matched cable with 800 mVp-p to 1.0 Vp-p swing.
7 SDO output Serial data complement output, driving a 75Ω AC-coupled back-matched cable paired with the true output.
8 VDD power_in Positive power supply, specified from +3.0 V to +3.6 V (3.3 V nominal).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage 4 V 4
Output Current 27 mA 4
Maximum Junction Temperature 125 °C 4
Storage Temperature Range -65 150 °C 4
Lead Temperature (Soldering 10 seconds) 300 °C Soldering 10 seconds 4
ESD Rating (HBM) 7 kV 4
ESD Rating (MM) 500 V 4
Supply Voltage Range (VDD -VSS) 3 3.6 V 4
Operating Free Air Temperature TA -40 85 °C 4
RBB Range (applied to VBB input) RBB 1.3 11.5 kΩ Note 6 4
Package Thermal Resistance, junction-to-ambient, surface mount AJE θJA 125 °C/W 4
Package Thermal Resistance, junction-to-case, surface mount AJE θJC 105 °C/W 4
Serial Driver Output Voltage (800 mVp-p) VSDO 720 800 880 mV RL = 75Ω 1%, RREF = 1.91 kΩ 1% (for 800 mVp-p), Figure 1 4
Serial Driver Output Voltage (1.0 Vp-p) VSDO 900 1000 1100 mV RL = 75Ω 1%, RREF = 1.5 kΩ 1% (for 1.0 Vp-p), Figure 1 4
Differential Input High Threshold VTH 0 100 mV VCM = +0.05V or +1.2V or +3.25V 4
Differential Input Low Threshold VTL -100 0 0 mV VDD = 3.3V 4
Common Mode Voltage Range VCMR 0.05 3.25 V VID = 100mV, VDD = 3.3V 4
Input Current IIN -10 10 µA VIN = 0V or +3.0V, VDD = 3.6V or 0V 4
Input Current Balance IINB 0.23 µA VIN = 0V or +3.0V, VDD = 3.6V or 0V, (Note 8) 4
Total Dynamic Power Supply Current (800 mVp-p) IDD 70 115 mA RL = 75Ω, RREF = 1.91 kΩ 1% (VSDO = 800 mVp-p @ 270 Mbps) 4
Total Dynamic Power Supply Current (1.0 Vp-p) IDD 85 130 mA RL = 75Ω, RREF = 1.5 kΩ 1% (VSDO = 1.0 Vp-p @ 622 Mbps) 4
Output Inductance LGEN 6 nH 4
Output Resistance RGEN 25 kΩ 4
VBB Current (800 mVp-p setting) IBB 250 µA RREF = 1.91 kΩ 1%, (Note 6) 4
VBB Current (1.0 Vp-p setting) IBB 315 µA RREF = 1.5 kΩ 1%, (Note 6) 4
Rise time, Fall time tr,tf 400 800 ps 20%-80%, (Notes 4, 5) 5
Output overshoot tos 5 % 5% 5
Output jitter tjit 25 ps Note 7 5
Propagation delay tpd 1.9 ns Note 5 5

CAD (KiCad official)

  • Symbol: CLC001AJE
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: clc001aje-etched.step / clc001aje-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clc001aje.step / clc001aje.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 9c4861571890b12a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF