# CJQ4953

**Changjiang Electronics Tech (CJ)** · Pre-ordered transistors · SOP-8

CJQ4953 from Changjiang Electronics Tech (CJ), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of the first P-channel MOSFET, with VDS rated -30 V and VGS rated ±20 V for the device. |
| 2 | G1 | input | Gate terminal of the first MOSFET, with gate-source voltage rated ±20 V (VGS). |
| 3 | S2 | passive | Source terminal of the second P-channel MOSFET, with VDS rated -30 V and VGS rated ±20 V for the device. |
| 4 | G2 | input | Gate terminal of the second MOSFET, with gate-source voltage rated ±20 V (VGS). |
| 5 | D2 | passive | Drain terminal of the second MOSFET, with continuous drain current ID rated -5 A (t≤10s). |
| 6 | D2 | passive | Drain terminal of the second MOSFET, with continuous drain current ID rated -5 A (t≤10s). |
| 7 | D1 | passive | Drain terminal of the first MOSFET, with continuous drain current ID rated -5 A (t≤10s). |
| 8 | D1 | passive | Drain terminal of the first MOSFET, with continuous drain current ID rated -5 A (t≤10s). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Changjiang Electronics Tech (CJ) |
| Package | SOP-8 |
| Category | Transistors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | -30 | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | -5 | A | t≤10s | 1 |
| Power Dissipation | PD |  |  | 1.25 | W | t≤10s | 1 |
| Junction Temperature | TJ |  |  | 150 | ℃ |  | 1 |
| Storage Temperature | TSTG | -55 |  | 150 | ℃ |  | 1 |
| Thermal Resistance from Junction to Ambient | RθJA |  |  | 100 | ℃/W | t≤10s | 1 |
| Drain-source breakdown voltage | V(BR)DSS | -30 |  |  | V | VGS =0V, ID =-250µA | 2 |
| Gate-threshold voltage | VGS(th) | -1 |  | -1.5 | V | VDS =VGS, ID =-250µA | 2 |
| Gate-body leakage | IGSS | -100 |  | 100 | nA | VDS =0V, VGS =±20V | 2 |
| Zero gate voltage drain current | IDSS |  |  | -1 | µA | VDS =-30V, VGS =0V | 2 |
| Drain-source on-resistance | RDS(on) |  | 50 | 60 | mΩ | VGS =-10V, ID =-4.9A | 2 |
| Drain-source on-resistance | RDS(on) |  | 66 | 90 | mΩ | VGS =-4.5V, ID =-3.7A | 2 |
| Forward transconductance | gfs | 6 |  |  | S | VDS =-10V, ID =-4.9A | 2 |
| Diode forward voltage | VSD |  |  | -1.2 | V | IS=-1.7A,VGS=0V | 2 |

## CAD (KiCad official)

- Symbol: `CJQ4953`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `cjq4953-etched.step` / `cjq4953-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cjq4953.step` / `cjq4953.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Changjiang Electronics Tech (CJ) datasheet](docs/cjq4953-datasheet.pdf) (5 pp, sha256 `127ee3c86f182113`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cjq4953-datasheet.pdf)