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CJE3139K
Public Made by Adomby adom
Changjing MOSFETs, SOT-523. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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cje3139k: specified limits as data (metadata.characteristics, 25 rows from the datasheet)
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18d ago
CJE3139K
Changjing · MOSFETs · SOT-523
CJE3139K from Changjing, in a SOT-523. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | input | Gate terminal of the CJE3139K P-channel MOSFET, with a gate-source voltage rating of ±12 V as listed in the maximum ratings. |
| 2 | SOURCE | passive | Source terminal of the P-channel MOSFET, serving as the reference for VGS; the datasheet gives no separate source-pin rating. |
| 3 | DRAIN | passive | Drain terminal of the P-channel MOSFET, rated for a drain-source voltage of -20 V and a continuous drain current of -0.66 A (note 1, surface-mounted on FR4 at minimum recommended pad size). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-523 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -20 | V | 1 | |||
| Gate-Source Voltage | VGS | -12 | 12 | V | 1 | ||
| Continuous Drain Current (note 1) | ID | -0.66 | A | 1 | |||
| Pulsed Drain Current | IDM | -1.2 | A | tp=10μs | 1 | ||
| Power Dissipation (note 1) | PD | 150 | mW | note 1: surface mounted on FR4, minimum recommended pad size | 1 | ||
| Thermal Resistance from Junction to Ambient (note 1) | RθJA | 833 | ℃/W | note 1: surface mounted on FR4, minimum recommended pad size | 1 | ||
| Junction Temperature | TJ | 150 | ℃ | 1 | |||
| Storage Temperature | TSTG | -55 | 150 | ℃ | 1 | ||
| Lead Temperature for Soldering Purposes | TL | 260 | ℃ | 1/8" from case for 10 s | 1 | ||
| Drain-source breakdown voltage | V(BR)DSS | -20 | V | VGS = 0V, ID = -250µA | 2 | ||
| Zero gate voltage drain current | IDSS | -1 | µA | VDS = -20V, VGS = 0V | 2 | ||
| Gate-body leakage current | IGSS | -20 | 20 | µA | VGS = ±10V, VDS = 0V | 2 | |
| Gate threshold voltage (note 2) | VGS(th) | -0.35 | -1.1 | V | VDS = VGS, ID = -250µA | 2 | |
| Drain-source on-resistance (note 2) | RDS(on) | 520 | mΩ | VGS = -4.5V, ID = -1A | 2 | ||
| Drain-source on-resistance (note 2) | RDS(on) | 700 | mΩ | VGS = -2.5V, ID = -0.8A | 2 | ||
| Drain-source on-resistance (note 2) | RDS(on) | 950 | mΩ | VGS = -1.8V, ID = -0.5A | 2 | ||
| Forward transconductance (note 2) | gFS | 1.2 | S | VDS = -10V, ID = -0.54A | 2 | ||
| Diode forward voltage | VSD | -1.2 | V | IS = -0.5A, VGS = 0V | 2 | ||
| Input capacitance | Ciss | 113 | 170 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 | |
| Output capacitance | Coss | 15 | 25 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 | |
| Reverse transfer capacitance | Crss | 9 | 15 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 | |
| Turn-on delay time (note 3) | td(on) | 9 | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 | ||
| Turn-on rise time (note 3) | tr | 5.8 | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 | ||
| Turn-off delay time (note 3) | td(off) | 32.7 | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 | ||
| Turn-off fall time (note 3) | tf | 20.3 | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 |
CAD (KiCad official)
- Symbol:
CJE3139K - Footprint:
Package_TO_SOT_SMD:SOT-523 - 3D model: SOT-523, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm nominal SOT-523 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
cje3139k-etched.step/cje3139k-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cje3139k.step/cje3139k.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Changjing datasheet (5 pp, sha256
2c1d1d8755b4b4a8, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CJE3139K
**Changjing** · MOSFETs · SOT-523
CJE3139K from Changjing, in a SOT-523. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | input | Gate terminal of the CJE3139K P-channel MOSFET, with a gate-source voltage rating of ±12 V as listed in the maximum ratings. |
| 2 | SOURCE | passive | Source terminal of the P-channel MOSFET, serving as the reference for VGS; the datasheet gives no separate source-pin rating. |
| 3 | DRAIN | passive | Drain terminal of the P-channel MOSFET, rated for a drain-source voltage of -20 V and a continuous drain current of -0.66 A (note 1, surface-mounted on FR4 at minimum recommended pad size). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-523 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -20 | | | V | | 1 |
| Gate-Source Voltage | VGS | -12 | | 12 | V | | 1 |
| Continuous Drain Current (note 1) | ID | -0.66 | | | A | | 1 |
| Pulsed Drain Current | IDM | -1.2 | | | A | tp=10μs | 1 |
| Power Dissipation (note 1) | PD | | | 150 | mW | note 1: surface mounted on FR4, minimum recommended pad size | 1 |
| Thermal Resistance from Junction to Ambient (note 1) | RθJA | | | 833 | ℃/W | note 1: surface mounted on FR4, minimum recommended pad size | 1 |
| Junction Temperature | TJ | | | 150 | ℃ | | 1 |
| Storage Temperature | TSTG | -55 | | 150 | ℃ | | 1 |
| Lead Temperature for Soldering Purposes | TL | | | 260 | ℃ | 1/8" from case for 10 s | 1 |
| Drain-source breakdown voltage | V(BR)DSS | -20 | | | V | VGS = 0V, ID = -250µA | 2 |
| Zero gate voltage drain current | IDSS | | | -1 | µA | VDS = -20V, VGS = 0V | 2 |
| Gate-body leakage current | IGSS | -20 | | 20 | µA | VGS = ±10V, VDS = 0V | 2 |
| Gate threshold voltage (note 2) | VGS(th) | -0.35 | | -1.1 | V | VDS = VGS, ID = -250µA | 2 |
| Drain-source on-resistance (note 2) | RDS(on) | | | 520 | mΩ | VGS = -4.5V, ID = -1A | 2 |
| Drain-source on-resistance (note 2) | RDS(on) | | | 700 | mΩ | VGS = -2.5V, ID = -0.8A | 2 |
| Drain-source on-resistance (note 2) | RDS(on) | | 950 | | mΩ | VGS = -1.8V, ID = -0.5A | 2 |
| Forward transconductance (note 2) | gFS | | 1.2 | | S | VDS = -10V, ID = -0.54A | 2 |
| Diode forward voltage | VSD | | | -1.2 | V | IS = -0.5A, VGS = 0V | 2 |
| Input capacitance | Ciss | | 113 | 170 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 |
| Output capacitance | Coss | | 15 | 25 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 |
| Reverse transfer capacitance | Crss | | 9 | 15 | pF | VDS = -16V, VGS = 0V, f = 1MHz | 2 |
| Turn-on delay time (note 3) | td(on) | | 9 | | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 |
| Turn-on rise time (note 3) | tr | | 5.8 | | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 |
| Turn-off delay time (note 3) | td(off) | | 32.7 | | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 |
| Turn-off fall time (note 3) | tf | | 20.3 | | ns | VGS = -4.5V, VDS = -10V, ID = -200mA, RGEN = 10Ω | 2 |
## CAD (KiCad official)
- Symbol: `CJE3139K`
- Footprint: `Package_TO_SOT_SMD:SOT-523`
- 3D model: SOT-523, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm nominal SOT-523 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `cje3139k-etched.step` / `cje3139k-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cje3139k.step` / `cje3139k.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Changjing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202724824596480) (5 pp, sha256 `2c1d1d8755b4b4a8`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cje3139k-datasheet.pdf)