CJC5357B

{
  "slug": "cjc5357b",
  "version": "0.1.0",
  "type": "component",
  "description": "ESHINE Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "data acquisition",
    "cjc5357b",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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  "component": {
    "mpn": "CJC5357B",
    "manufacturer": "ESHINE",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603004007870701568",
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      "lbr": "cjc5357b.lbr"
    },
    "distributor_links": {
      "lcsc": "C7431489"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T00:01:32Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AINR",
        "type": "input",
        "description": "Rch single-ended analog input, internally biased to the common voltage through about 20 kΩ; leave unused input open."
      },
      {
        "number": "2",
        "name": "AINL",
        "type": "input",
        "description": "Lch single-ended analog input, internally biased to the common voltage through about 20 kΩ; leave unused input open."
      },
      {
        "number": "3",
        "name": "CKS1",
        "type": "input",
        "description": "Mode select 1 pin, which must be connected to VA or AGND and must not be left floating."
      },
      {
        "number": "4",
        "name": "VCOM",
        "type": "output",
        "description": "Common voltage output at VA/2 for the ADC input bias, normally decoupled to AGND with a 0.1 µF ceramic capacitor plus 0.47 µF, and no load current may be drawn."
      },
      {
        "number": "5",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground, which must be connected to the same analog ground plane as DGND."
      },
      {
        "number": "6",
        "name": "VA",
        "type": "power_in",
        "description": "Analog power supply of 2.7 to 3.6 V (3.3 V typical), which sets the analog input range."
      },
      {
        "number": "7",
        "name": "VD",
        "type": "power_in",
        "description": "Digital power supply of 2.7 to 3.6 V."
      },
      {
        "number": "8",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground, which must be connected to the same analog ground plane as AGND."
      },
      {
        "number": "9",
        "name": "SDTO",
        "type": "output",
        "description": "Audio serial data output, clocked out on the falling edge of SCLK, and outputs L in power-down mode."
      },
      {
        "number": "10",
        "name": "LRCK",
        "type": "bidirectional",
        "description": "Output channel clock, which is an input in slave mode and an output in master mode, and outputs L in master mode during power-down; sampling rate range is 4 to 96 kHz."
      },
      {
        "number": "11",
        "name": "MCLK",
        "type": "input",
        "description": "Master clock input from 1.024 to 36.684 MHz, which must be present unless PDN is L."
      },
      {
        "number": "12",
        "name": "SCLK",
        "type": "bidirectional",
        "description": "Audio serial data clock, which is an output fixed at 64fs in master mode and outputs L in master mode during power-down."
      },
      {
        "number": "13",
        "name": "PDN",
        "type": "input",
        "description": "Power-down pin, where H powers up the device and L powers it down and resets the digital filter; the device is reset by taking PDN low."
      },
      {
        "number": "14",
        "name": "DIF",
        "type": "input",
        "description": "Audio interface format select, where H selects 24-bit I2S compatible format and L selects 24-bit MSB justified format."
      },
      {
        "number": "15",
        "name": "CKS2",
        "type": "input",
        "description": "Mode select 2 pin, which sets MCLK/SCLK ratio, HPF and master/slave mode together with CKS0 and CKS1 per Table 2, and must not be left floating."
      },
      {
        "number": "16",
        "name": "CKS0",
        "type": "input",
        "description": "Mode select 0 pin, which sets mode together with CKS1 and CKS2 per Table 2, and must not be left floating."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and names come from the Section 5 pin table (page 5). The Figure 2 top-view image has no; The Table 2 mode-select matrix (CKS2-0 meaning) is an image and is not in the text, so the CKS0/CKS2; The datasheet gives two different full-scale input values: Note 4 says Vin = 0.6×VA Vpp (1.98 V at 3"
        ],
        "pages_sent": 17,
        "cost_usd": 0.0565,
        "at": "2026-10-17T23:59:17"
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        "pages": 17,
        "sha256": "7d003a022171dff4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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}