component
CJC5357B
Public Made by Adomby adom
ESHINE Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCJC5357B
ESHINE · Analog To Digital Converters (ADC) · TSSOP-16
CJC5357B from ESHINE, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AINR | input | Rch single-ended analog input, internally biased to the common voltage through about 20 kΩ; leave unused input open. |
| 2 | AINL | input | Lch single-ended analog input, internally biased to the common voltage through about 20 kΩ; leave unused input open. |
| 3 | CKS1 | input | Mode select 1 pin, which must be connected to VA or AGND and must not be left floating. |
| 4 | VCOM | output | Common voltage output at VA/2 for the ADC input bias, normally decoupled to AGND with a 0.1 µF ceramic capacitor plus 0.47 µF, and no load current may be drawn. |
| 5 | AGND | power_in | Analog ground, which must be connected to the same analog ground plane as DGND. |
| 6 | VA | power_in | Analog power supply of 2.7 to 3.6 V (3.3 V typical), which sets the analog input range. |
| 7 | VD | power_in | Digital power supply of 2.7 to 3.6 V. |
| 8 | DGND | power_in | Digital ground, which must be connected to the same analog ground plane as AGND. |
| 9 | SDTO | output | Audio serial data output, clocked out on the falling edge of SCLK, and outputs L in power-down mode. |
| 10 | LRCK | bidirectional | Output channel clock, which is an input in slave mode and an output in master mode, and outputs L in master mode during power-down; sampling rate range is 4 to 96 kHz. |
| 11 | MCLK | input | Master clock input from 1.024 to 36.684 MHz, which must be present unless PDN is L. |
| 12 | SCLK | bidirectional | Audio serial data clock, which is an output fixed at 64fs in master mode and outputs L in master mode during power-down. |
| 13 | PDN | input | Power-down pin, where H powers up the device and L powers it down and resets the digital filter; the device is reset by taking PDN low. |
| 14 | DIF | input | Audio interface format select, where H selects 24-bit I2S compatible format and L selects 24-bit MSB justified format. |
| 15 | CKS2 | input | Mode select 2 pin, which sets MCLK/SCLK ratio, HPF and master/slave mode together with CKS0 and CKS1 per Table 2, and must not be left floating. |
| 16 | CKS0 | input | Mode select 0 pin, which sets mode together with CKS1 and CKS2 per Table 2, and must not be left floating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ESHINE |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Power Supply | VA | -0.3 | 6 | V | 5 | ||
| Digital Power Supply | VD | -0.3 | 6 | V | 5 | ||
| AGND to DGND voltage difference | △GND | 0.3 | V | AGND and DGND tied to same analog ground plane (Note 2) | 5 | ||
| Input Current (any pin except supplies) | IIN | -10 | 10 | mA | Any pin except supplies | 5 | |
| Analog Input Voltage (AINL, AINR, CKS1 pins) | VINA | -0.3 | 0.3 | V | Max printed as VA+0.3 | 5 | |
| Digital Input Voltage (all digital inputs except CKS1) | VIND | -0.3 | 0.3 | V | Max printed as VD+0.3 | 5 | |
| Ambient Temperature (commercial) | Ta | -20 | 85 | ℃ | Commercial grade | 5 | |
| Ambient Temperature (industrial) | Ta | -40 | 85 | ℃ | Industrial grade | 5 | |
| Storage Temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| Analog Power Supply (recommended) | VA | 2.7 | 3.3 | 3.6 | V | AGND, DGND = 0 V | 6 |
| Digital Power Supply (recommended) | VD | 2.7 | 3.3 | 3.6 | V | AGND, DGND = 0 V | 6 |
| High-level Input Voltage | VIH | 70 | %VD | CMOS level mode, VA,VD=2.7~5.5V | 8 | ||
| Low-level Input Voltage | VIL | 30 | %VD | CMOS level mode, VA,VD=2.7~5.5V | 8 | ||
| High-level Output Voltage | VOH | 0.5 | V | Iout=−1mA; min printed as VD−0.5 | 8 | ||
| Low-level Output Voltage | VOL | 0.5 | V | Iout=1mA | 8 | ||
| Input Leakage Current | Iin | -10 | 10 | μA | 8 | ||
| Master Clock Frequency | fCLK | 1.024 | 36.684 | MHz | CL=20pF; VA,VD=2.7~3.6V | 8 | |
| LRCK Frequency | fs | 4 | 96 | kHZ | 8 | ||
| Duty Cycle (slave mode) | 45 | 55 | % | Slave mode | 8 | ||
| SCLK↑ to LRCK edge (master mode) | tMSLR | -20 | 20 | ns | SCLK↓ to LRCK, master mode | 8 | |
| Input Resistance (fs=48kHz) | 13 | 20 | kΩ | fs=48kHz | 6 | ||
| Input Resistance (fs=96kHz) | 9 | 14 | kΩ | fs=96kHz | 6 | ||
| Interchannel Isolation | 94 | 100 | dB | 6 | |||
| Interchannel Gain Mismatch | 0.1 | 0.5 | dB | 6 | |||
| Power Supply Current, VA (normal operation) | VA | 7 | 8.5 | mA | Normal operation | 6 | |
| Power Supply Current, VD (fs=48kHz) | VD | 1.5 | 3 | mA | fs=48kHz (Note 6: VD=[email protected]) | 6 | |
| Power Supply Current, VD (fs=96kHz) | VD | 2 | 4 | mA | fs=96kHz (Note 7: VD=[email protected]) | 6 | |
| Power Supply Current, power-down mode | VA+VD | 1 | 100 | μA | PDN pin = L | 6 | |
| ADC Digital Filter passband ±0.02 dB (fs=48kHz) | PB | 0 | 20 | kHz | ±0.02 dB, fs=48kHz | 7 | |
| ADC Digital Filter stopband (fs=48kHz) | SB | 28 | kHz | fs=48kHz | 7 | ||
| ADC Digital Filter passband ripple (fs=48kHz) | PR | -0.02 | 0.02 | dB | ±0.02 dB, fs=48kHz | 7 | |
| ADC Digital Filter stopband attenuation (fs=48kHz) | SA | 66 | dB | fs=48kHz | 7 | ||
| ADC Digital Filter passband ±0.02 dB (fs=96kHz) | PB | 0 | 20 | kHz | ±0.02 dB, fs=96kHz | 7 | |
| ADC Digital Filter stopband (fs=96kHz) | SB | 56 | kHz | fs=96kHz | 7 | ||
| ADC Digital Filter stopband attenuation (fs=96kHz) | SA | 66 | dB | fs=96kHz | 7 |
CAD (KiCad official)
- Symbol:
CJC5357B - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cjc5357b-etched.step/cjc5357b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cjc5357b.step/cjc5357b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ESHINE datasheet (17 pp, sha256
7d003a022171dff4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).