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CJC5340

Public Made by Adom

by adom

ESHINE Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CJC5340

ESHINE · Analog To Digital Converters (ADC) · TSSOP-16

CJC5340 from ESHINE, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 M0 input Mode selection input that, together with M1 (pin 16), selects clock master single-, double- or quad-speed mode or clock slave mode per Table 2.
2 MCLK input Master clock input that clocks the delta-sigma modulator and digital filters, with MCLK/LRCK ratios per Table 3 and a 40% to 60% pulse duty cycle.
3 VL power_in Logic power supply for the digital inputs and outputs, specified at 3 V to 3.6 V (3.3 V typical).
4 SDOUT output Serial audio data output carrying two's complement data; at start-up its logic level selects I²S format (10 kΩ pull-up to VL) or left-justified format (10 kΩ pull-down to GND).
5 GND power_in Ground reference that must be connected to analog ground.
6 VD power_in Digital power supply for the digital filter section, specified at 3 V to 3.6 V.
7 SCLK bidirectional Serial clock for the audio interface, an output in clock master mode and an input in clock slave mode, recommended at 64x Fs.
8 LRCK bidirectional Left/right clock that selects the active channel, an output in clock master mode and an input in clock slave mode, equal to Fs.
9 /RST input Reset input; the device enters a low power mode when this pin is low.
10 AINL input Left-channel analog input whose full-scale level is specified in the Analog Characteristics table.
11 VQ output Quiescent voltage filter connection for the internal quiescent reference voltage, whose decoupling capacitors must be placed close to the pin per Section 9.
12 AINR input Right-channel analog input whose full-scale level is specified in the Analog Characteristics table.
13 VA power_in Analog power supply for the analog section, specified at 3 V to 3.6 V.
14 GND power_in Ground reference that must be connected to analog ground.
15 FILT+ output Positive voltage reference output for the internal sampling circuits, which requires decoupling capacitors placed close to the pin per Section 9.
16 M1 input Mode selection input that, together with M0 (pin 1), selects the clock master or slave operating mode per Table 2.

Key specifications

Parameter Value
Manufacturer ESHINE
Package TSSOP-16
Category Data Acquisition
Pins 16

CAD (KiCad official)

  • Symbol: CJC5340
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cjc5340-etched.step / cjc5340-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cjc5340.step / cjc5340.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ESHINE datasheet (19 pp, sha256 f01a0fe739f4f3c2, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF