# CEM6867

**CET(Chino-Excel Tech)** · MOSFETs · SOP-8

CEM6867 from CET(Chino-Excel Tech), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of the Q1 P-channel MOSFET; the device is rated VDS = -60 V, VGS = ±20 V, and ID = -3.1 A continuous. |
| 2 | G1 | input | Gate of the Q1 P-channel MOSFET; gate-source voltage is rated ±20 V (VGS). |
| 3 | S2 | passive | Source of the Q2 P-channel MOSFET; the device is rated VDS = -60 V, VGS = ±20 V, and ID = -3.1 A continuous. |
| 4 | G2 | input | Gate of the Q2 P-channel MOSFET; gate-source voltage is rated ±20 V (VGS). |
| 5 | D2 | passive | Drain of the Q2 P-channel MOSFET; drain-source voltage is rated -60 V (VDS). |
| 6 | D2 | passive | Drain of the Q2 P-channel MOSFET (internally tied to pin 5); drain-source voltage is rated -60 V (VDS). |
| 7 | D1 | passive | Drain of the Q1 P-channel MOSFET; drain-source voltage is rated -60 V (VDS). |
| 8 | D1 | passive | Drain of the Q1 P-channel MOSFET (internally tied to pin 7); drain-source voltage is rated -60 V (VDS). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CET(Chino-Excel Tech) |
| Package | SOP-8 |
| Category | Transistors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | -60 | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Drain Current-Continuous | ID |  |  | -3.1 | A |  | 1 |
| Drain Current-Pulsed | IDM |  |  | -12 | A |  | 1 |
| Maximum Power Dissipation | PD |  |  | 2 | W |  | 1 |
| Operating and Store Temperature Range | TJ,Tstg | -55 |  | 150 | C |  | 1 |
| Thermal Resistance, Junction-to-Ambient | RθJA |  |  | 62.5 | C/W |  | 1 |
| Drain-Source Breakdown Voltage | BVDSS | -60 |  |  | V | VGS = 0V, ID = -250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | µA | VDS = -60V, VGS = 0V | 2 |
| Gate Body Leakage Current, Forward | IGSSF |  |  | 100 | nA | VGS = 20V, VDS = 0V | 2 |
| Gate Body Leakage Current, Reverse | IGSSR |  |  | -100 | nA | VGS = -20V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 |  | -3 | V | VGS = VDS, ID = -250µA | 2 |
| Static Drain-Source On-Resistance | RDS(on) |  | 100 | 130 | mΩ | VGS = -10V, ID = -3.1A | 2 |
| Static Drain-Source On-Resistance | RDS(on) |  |  | 170 | mΩ | VGS = -4.5V, ID = -2.8A | 2 |
| Drain-Source Diode Forward Current | IS |  |  | -1.5 | A |  | 2 |
| Drain-Source Diode Forward Voltage | VSD |  |  | -1.2 | V | VGS = 0V, IS = -1.5A | 2 |

## CAD (KiCad official)

- Symbol: `CEM6867`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `cem6867-etched.step` / `cem6867-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cem6867.step` / `cem6867.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CET(Chino-Excel Tech) datasheet](docs/cem6867-datasheet.pdf) (4 pp, sha256 `e469e88a08b20a66`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cem6867-datasheet.pdf)