component
CDCVF25084PWR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
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{
"slug": "cdcvf25084pwr",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Clock Buffers, Drivers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"rtc-clock chip",
"cdcvf25084pwr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cdcvf25084pwr.kicad_sym",
"cdcvf25084pwr.kicad_mod",
"cdcvf25084pwr.glb",
"cdcvf25084pwr.step",
"cdcvf25084pwr.lbr",
"docs/hero.png",
"docs/cdcvf25084pwr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cdcvf25084pwr-hero.glb",
"cdcvf25084pwr-hero.overlay.json",
"cdcvf25084pwr-etched.glb"
],
"component": {
"mpn": "CDCVF25084PWR",
"manufacturer": "Texas Instruments",
"package": "TSSOP-16",
"pin_count": 16,
"category": "RTC/Clock Chip",
"subcategory": "Clock Buffers, Drivers",
"datasheet": "https://www.ti.com/lit/ds/symlink/cdcvf25084.pdf",
"parts": {
"symbol": "cdcvf25084pwr.kicad_sym",
"footprint": "cdcvf25084pwr.kicad_mod",
"model_3d": "cdcvf25084pwr-hero.glb",
"model_3d_plain": "cdcvf25084pwr-etched.glb",
"model_3d_step": "cdcvf25084pwr-etched.step",
"model_3d_step_plain": "cdcvf25084pwr.step",
"lbr": "cdcvf25084pwr.lbr"
},
"distributor_links": {
"lcsc": "C2864686",
"digikey": "CDCVF25084PWR-ND",
"mouser": "595-CDCVF25084PWR"
},
"distributor_check": {
"checked_at": "2026-10-31T00:22:03Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "CDCVF25084PWR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-CDCVF25084PWR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "CLKIN",
"type": "input",
"description": "Clock input that provides the reference signal to the integrated PLL and must have a fixed frequency and phase for the PLL to lock, with an input clock frequency range of 2.5 MHz to 45 MHz and duty cycle of 40% to 60%."
},
{
"number": "2",
"name": "1Y0",
"type": "output",
"description": "Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "3",
"name": "1Y1",
"type": "output",
"description": "Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "4",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the supply voltage range is 3 V to 3.6 V (3.3 V nominal)."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Ground pin."
},
{
"number": "6",
"name": "2Y0",
"type": "output",
"description": "Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "7",
"name": "2Y1",
"type": "output",
"description": "Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "8",
"name": "S2",
"type": "input",
"description": "Mode select input that, together with S1, selects the operating mode (PLL, PLL bypass, or outputs Hi-Z with PLL shutdown) per the function table."
},
{
"number": "9",
"name": "S1",
"type": "input",
"description": "Mode select input that, together with S2, selects the operating mode (PLL, PLL bypass, or outputs Hi-Z with PLL shutdown) per the function table."
},
{
"number": "10",
"name": "2Y2",
"type": "output",
"description": "Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "11",
"name": "2Y3",
"type": "output",
"description": "Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "12",
"name": "GND",
"type": "power_in",
"description": "Ground pin."
},
{
"number": "13",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the supply voltage range is 3 V to 3.6 V (3.3 V nominal)."
},
{
"number": "14",
"name": "1Y2",
"type": "output",
"description": "Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "15",
"name": "1Y3",
"type": "output",
"description": "Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz."
},
{
"number": "16",
"name": "FBIN",
"type": "input",
"description": "PLL feedback input that must be wired to one of the outputs to complete the internal PLL loop, giving nominally zero delay from CLKIN to the outputs."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin positions 1-8 (left side) and 9-16 (right side) were taken from the TOP VIEW drawing text on pag"
],
"pages_sent": 17,
"cost_usd": 0.0655,
"at": "2026-10-31T00:21:50"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/cdcvf25084.pdf",
"pages": 17,
"sha256": "3e71133234263be7",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cdcvf25084pwr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
5.0,
1.1
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cdcvf25084pwr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
5.0,
1.1
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "6e600ea19a79449d506aa92e7c89ebe59c8896a6d48a94d071d366e6bbd284cc",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "PW0016A",
"source_page": 14,
"D": {
"nom_mm": 5.0,
"range_mm": [
4.9,
5.1
]
},
"E1": {
"nom_mm": 4.4,
"range_mm": [
4.3,
4.5
]
},
"E": {
"nom_mm": 6.4,
"range_mm": [
6.2,
6.6
]
},
"e": {
"nom_mm": 0.65,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.2,
"range_mm": [
null,
1.2
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "cdcvf25084pwr.step",
"verdict": "PASS",
"reasons": [
"height and body within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}