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CDCVF25084PWR

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Texas Instruments Clock Buffers, Drivers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdcvf25084pwrfactory-2.0.0extractor-text

Verified CDCVF25084PWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCVF25084PWR · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 17-page datasheet
  • ✓distributor: lcsc C2864686, digikey CDCVF25084PWR-ND, mouser 595-CDCVF25084PWR
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-dnmymq00/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.14)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdcvf25084pwr.kicad_sym✓ cdcvf25084pwr.kicad_mod✓ cdcvf25084pwr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cdcvf25084pwr: viewers · Ray
cdcvf25084pwr-etched.glb Publish 0.1.0 · Ray
cdcvf25084pwr-etched.step cdcvf25084pwr: factory component page (tier=mfr) · Ray
cdcvf25084pwr-hero.glb cdcvf25084pwr: hero GLB from the etched model (keeps the MPN mark) · Ray
cdcvf25084pwr-hero.overlay.json Publish 0.1.0 · Ray
cdcvf25084pwr.glb Publish 0.1.0 · Ray
cdcvf25084pwr.kicad_mod Publish 0.1.0 · Ray
cdcvf25084pwr.kicad_sym Publish 0.1.0 · Ray
cdcvf25084pwr.lbr Publish 0.1.0 · Ray
cdcvf25084pwr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray

CDCVF25084PWR

Texas Instruments · Clock Buffers, Drivers · TSSOP-16

CDCVF25084PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input Clock input that provides the reference signal to the integrated PLL and must have a fixed frequency and phase for the PLL to lock, with an input clock frequency range of 2.5 MHz to 45 MHz and duty cycle of 40% to 60%.
2 1Y0 output Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
3 1Y1 output Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
4 VDD power_in Power supply pin; the supply voltage range is 3 V to 3.6 V (3.3 V nominal).
5 GND power_in Ground pin.
6 2Y0 output Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
7 2Y1 output Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
8 S2 input Mode select input that, together with S1, selects the operating mode (PLL, PLL bypass, or outputs Hi-Z with PLL shutdown) per the function table.
9 S1 input Mode select input that, together with S2, selects the operating mode (PLL, PLL bypass, or outputs Hi-Z with PLL shutdown) per the function table.
10 2Y2 output Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
11 2Y3 output Bank 2 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
12 GND power_in Ground pin.
13 VDD power_in Power supply pin; the supply voltage range is 3 V to 3.6 V (3.3 V nominal).
14 1Y2 output Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
15 1Y3 output Bank 1 clock output that is a low-skew copy of CLKIN with an integrated 25-Ω series-damping resistor, specified for output frequency 10 MHz to 180 MHz.
16 FBIN input PLL feedback input that must be wired to one of the outputs to complete the internal PLL loop, giving nominally zero delay from CLKIN to the outputs.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category RTC/Clock Chip
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 3 3.3 3.6 V 4
Low level input voltage VIL 0.8 V 4
High level input voltage VIH 2 V 4
Input voltage VI 0 3.6 V 4
High-level output current IOH -12 mA 4
Low-level output current IOL 12 mA 4
Operating free-air temperature TA -40 85 °C 4
Input clock frequency fCLKIN 2.5 45 MHz 4
Input clock duty cycle 40 60 % 4
Clock frequency fclkout 10 180 MHz CL = 15 pF 4
Supply voltage range VDD -0.5 4.6 V 4
Input voltage range VI -0.5 4.6 V see Notes 1 and 2 4
Output voltage range VO -0.5 V max printed as VDD + 0.5 V; see Notes 1 and 2 4
Input clamp current IIK -50 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous total output current IO -50 50 mA VO = 0 to VDD 4
Storage temperature range Tstg -65 150 °C 4
Input voltage VIK -1.2 V VDD = 3 V, II = -18 mA 5
Input current II -5 5 µA VI = 0 V or VDD 5
Power-down current IPD 100 µA fCLKIN = 0 MHz, VDD = 3.3 V 5
Dynamic current IDD 60 80 mA fout = 80 MHz, CL = 15 pF 5
Output 3-state current IOZ -5 5 µA Vo = 0 V or VDD, VDD = 3.6 V 5
High-level output voltage VOH 2.1 V VDD = 3 V, IOH = -12 mA 5
High-level output voltage VOH 2.4 V VDD = 3 V, IOH = -6 mA 5
Low-level output voltage VOL 0.2 V VDD = min to max, IOL = 100 µA 5
Low-level output voltage VOL 0.8 V VDD = 3 V, IOL = 12 mA 5
Low-level output voltage VOL 0.55 V VDD = 3 V, IOL = 6 mA 5
High-level output current IOH -24 mA VDD = 3 V, VO = 1 V 5
High-level output current IOH -30 mA VDD = 3.3 V, VO = 1.65 V 5
High-level output current IOH -15 mA VDD = 3.6 V, VO = 3.135 V 5
Low-level output current IOL 26 mA VDD = 3 V, VO = 1.95 V 5
Low-level output current IOL 33 mA VDD = 3.3 V, VO = 1.65 V 5
Low-level output current IOL 14 mA VDD = 3.6 V, VO = 0.4 V 5
PLL lock time t(lock) 2 µs fout = 100 MHz 6
Phase offset (CLKIN to FBIN) t(phoffset) -200 200 ps fout = 40 MHz to 75 MHz, Vth = VDD/2 6
Phase offset (CLKIN to FBIN) t(phoffset) -100 100 ps fout = 75 MHz to 180 MHz, Vth = VDD/2 6
Propagation delay tPLH, tPHL 2.3 4.5 ns S2 = High, S1 = Low (PLL bypass mode) 6
Output skew (Yn to Yn) tsk(o) 75 150 ps See Figure 3 6
Part-to-part skew tsk(pp) 900 ps PLL bypass mode 6
Part-to-part skew (low-to-high transition) tsk(pp) 350 ps PLL mode, fout = 40 MHz to 75 MHz 6
Part-to-part skew (low-to-high transition) tsk(pp) 300 ps PLL mode, fout = 75 MHz to 180 MHz 6
Jitter (cycle to cycle) tjit(cc) -220 220 ps fout = 40 MHz to 75 MHz 6
Jitter (cycle to cycle) tjit(cc) -120 120 ps fout = 75 MHz to 180 MHz 6
Period jitter tjit(per) 260 ps fout = 40 MHz to 75 MHz 6
Period jitter tjit(per) 140 ps fout = 75 MHz to 180 MHz 6
Phase jitter, peak-to-peak tjit(θ) -110 110 ps fout = 75 MHz to 180 MHz, peak-to-peak (see Note 6) 6
Phase jitter, RMS tjit(θ) 26 ps fout = 75 MHz to 180 MHz, RMS (see Note 6) 6
Output duty cycle odc 45 55 % fout = 10 MHz to 180 MHz 6
Pulse skew tsk(p) 0.3 ns S2 = High, S1 = low (PLL bypass mode) 6
Rise / fall time rate tr, tf 1 3 V/ns See Figure 4 6
Input capacitance at FBIN, CLKIN CI 4 pF VI = 0 V or VDD 5
Input capacitance at S1, S2 CI 2.2 pF VI = 0 V or VDD 5
Output capacitance CO 3 pF VI = 0 V or VDD 5
Package thermal impedance (PW package) θJA 147 °C/W PW package (see Note 3) 4

CAD (KiCad official)

  • Symbol: CDCVF25084PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cdcvf25084pwr-etched.step / cdcvf25084pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcvf25084pwr.step / cdcvf25084pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 3e71133234263be7, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF