component
CDCS501PWR
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CDCS501PWR
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-8
CDCS501PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | LVCMOS clock input, specified for 40 MHz to 108 MHz with VIL at most 0.3 VDD and VIH at least 0.7 VDD. |
| 2 | SSC_SEL 0 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 1 and SSC_SEL 2 when SSC_ON is low. |
| 3 | SSC_SEL 1 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 0 and SSC_SEL 2 when SSC_ON is low. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SSC_ON | input | Active-low SSC on/off pin with internal pull-down; when high the spread-spectrum generator is off and the LVCMOS input is passed to OUT. |
| 6 | OUT | output | LVCMOS clock output with IOH/IOL up to 12 mA and a 15 pF output load test condition. |
| 7 | SSC_SEL 2 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 0 and SSC_SEL 1 when SSC_ON is low. |
| 8 | VDD | power_in | 3.3 V power supply, recommended range 3.0 V to 3.6 V, absolute maximum 4.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
CDCS501PWR - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
cdcs501pwr-etched.step/cdcs501pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdcs501pwr.step/cdcs501pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
acd7460ee8fe2a69, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CDCS501PWR
**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-8
CDCS501PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | LVCMOS clock input, specified for 40 MHz to 108 MHz with VIL at most 0.3 VDD and VIH at least 0.7 VDD. |
| 2 | SSC_SEL 0 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 1 and SSC_SEL 2 when SSC_ON is low. |
| 3 | SSC_SEL 1 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 0 and SSC_SEL 2 when SSC_ON is low. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SSC_ON | input | Active-low SSC on/off pin with internal pull-down; when high the spread-spectrum generator is off and the LVCMOS input is passed to OUT. |
| 6 | OUT | output | LVCMOS clock output with IOH/IOL up to 12 mA and a 15 pF output load test condition. |
| 7 | SSC_SEL 2 | input | Spread selection pin with internal pull-up that sets the spread amount together with SSC_SEL 0 and SSC_SEL 1 when SSC_ON is low. |
| 8 | VDD | power_in | 3.3 V power supply, recommended range 3.0 V to 3.6 V, absolute maximum 4.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `CDCS501PWR`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `cdcs501pwr-etched.step` / `cdcs501pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcs501pwr.step` / `cdcs501pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcs501.pdf) (13 pp, sha256 `acd7460ee8fe2a69`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cdcs501pwr-datasheet.pdf)