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CDCM6208V1FRGZR

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdcm6208v1frgzrfactory-2.0.0extractor-text

Verified CDCM6208V1FRGZR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCM6208V1FRGZR · VQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 88-page datasheet
  • ✓distributor: lcsc C2664407, digikey CDCM6208V1FRGZR-ND, mouser 595-CDCM6208V1FRGZR
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-yra618jj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.85)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdcm6208v1frgzr.kicad_sym✓ cdcm6208v1frgzr.kicad_mod✓ cdcm6208v1frgzr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cdcm6208v1frgzr: viewers · Ray
cdcm6208v1frgzr-etched.glb Publish 0.1.0 · Ray
cdcm6208v1frgzr-etched.step cdcm6208v1frgzr: factory component page (tier=mfr) · Ray
cdcm6208v1frgzr-hero.glb cdcm6208v1frgzr: hero GLB from the etched model (keeps the MPN mark) · Ray
cdcm6208v1frgzr-hero.overlay.json Publish 0.1.0 · Ray
cdcm6208v1frgzr.glb Publish 0.1.0 · Ray
cdcm6208v1frgzr.kicad_mod Publish 0.1.0 · Ray
cdcm6208v1frgzr.kicad_sym Publish 0.1.0 · Ray
cdcm6208v1frgzr.lbr Publish 0.1.0 · Ray
cdcm6208v1frgzr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 49 pins · Ray

CDCM6208V1FRGZR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-48-EP(7x7)

CDCM6208V1FRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI_MODE0 input Serial interface mode select bit 0 (LVCMOS, 50kΩ pull-down); SI_MODE[1:0]=00 SPI, 01 I2C, 10 pin mode, 11 reserved.
2 SDI/SDA/PIN1 bidirectional SPI serial data input, I2C bidirectional serial data (open-drain output, needs pull-up), or control pin 1 in pin mode.
3 SDO/AD0/PIN2 bidirectional SPI serial data output, I2C address offset bit 0 input, or control pin 2 in pin mode (LVCMOS, no pull resistor).
4 SCS/AD1/PIN3 input SPI latch enable, I2C address offset bit 1 input, or control pin 3 in pin mode (LVCMOS, no pull resistor).
5 SCL/PIN4 input SPI/I2C clock input or control pin 4 in pin mode (LVCMOS, no pull resistor).
6 REF_SEL input Manual reference selection for PLL (LVCMOS, 50kΩ pull-up): low selects PRI_REF, high selects SEC_REF (when Reg 4.12 = 1).
7 VDD_PRI_REF power_in Analog supply for the reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connect to VDD_SEC_REF.
8 PRI_REFP input Universal primary reference input, positive.
9 PRI_REFN input Universal primary reference input, negative.
10 VDD_SEC_REF power_in Analog supply for the reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connect to VDD_PRI_REF; may be connected to GND if the secondary input buffer is disabled (Reg 4 bit 5 = 0).
11 SEC_REFP input Universal secondary reference input, positive.
12 SEC_REFN input Universal secondary reference input, negative.
13 VDD_Y0_Y1 power_in Supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of 2 pins).
14 Y0_P output Universal output 0, positive terminal.
15 Y0_N output Universal output 0, negative terminal.
16 Y1_N output Universal output 1, negative terminal.
17 Y1_P output Universal output 1, positive terminal.
18 VDD_Y0_Y1 power_in Supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of 2 pins).
19 VDD_Y2_Y3 power_in Supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of 2 pins).
20 Y2_P output Universal output 2, positive terminal.
21 Y2_N output Universal output 2, negative terminal.
22 Y3_N output Universal output 3, negative terminal.
23 Y3_P output Universal output 3, positive terminal.
24 VDD_Y2_Y3 power_in Supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of 2 pins).
25 Y4_N output Universal output 4, negative terminal.
26 Y4_P output Universal output 4, positive terminal.
27 VDD_Y4 power_in Supply for output 4, set to 1.8 V, 2.5 V or 3.3 V.
28 Y5_N output Universal output 5, negative terminal.
29 Y5_P output Universal output 5, positive terminal.
30 VDD_Y5 power_in Supply for output 5, set to 1.8 V, 2.5 V or 3.3 V.
31 VDD_Y6 power_in Supply for output 6, set to 1.8 V, 2.5 V or 3.3 V.
32 Y6_P output Universal output 6, positive terminal.
33 Y6_N output Universal output 6, negative terminal.
34 VDD_Y7 power_in Supply for output 7, set to 1.8 V, 2.5 V or 3.3 V.
35 Y7_P output Universal output 7, positive terminal.
36 Y7_N output Universal output 7, negative terminal.
37 VDD_PLL1 power_in Analog power supply connection for the PLL.
38 VDD_PLL2 power_in Analog supply sensitive to power supply noise; can be combined with the VDD_VCO supply.
39 VDD_VCO power_in Analog supply for PLL/VCO, sensitive to power supply noise; can be combined with the VDD_PLL2 supply.
40 REG_CAP passive Regulator capacitor pin; connect a 10 µF capacitor with ESR below 1 Ω to GND at frequencies above 100 kHz.
41 ELF passive External loop filter pin for the PLL.
42 SYNCN input Active-low synchronization input (LVCMOS, 50kΩ pull-up); outputs synchronize on a low-to-high transition and SYNCN held low disables all outputs.
43 PDN input Active-low power-down (LVCMOS, 50kΩ pull-up); low disables the device and minimizes current, and exiting resets the device and defaults all registers.
44 RESETN/PWR input Active-low reset in SPI/I2C mode (LVCMOS, 50kΩ pull-up); in pin mode selects supply setting, 0 = 1.8 V, 1 = 2.5/3.3 V.
45 STATUS1/PIN0 bidirectional LVCMOS status output 1 in SPI/I2C modes (no pull resistor) or control pin 0 input in pin mode.
46 STATUS0 output LVCMOS status output 0.
47 SI_MODE1 input Serial interface mode select bit 1 (LVCMOS, 50kΩ pull-up); SI_MODE[1:0]=00 SPI, 01 I2C, 10 pin mode, 11 reserved.
48 DVDD power_in Digital power supply and reference supply voltage for all control inputs; must match the expected input signal swing of the control inputs.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category RTC/Clock Chip
Pins 49

CAD (KiCad official)

  • Symbol: CDCM6208V1FRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: cdcm6208v1frgzr-etched.step / cdcm6208v1frgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm6208v1frgzr.step / cdcm6208v1frgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (88 pp, sha256 1a74c4b03652e0b7, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF