component
CDCLVC1106PWR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
cdclvc1106pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
f9189e2
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{
"schema_version": 1,
"type": "component",
"slug": "cdclvc1106pwr",
"title": "CDCLVC1106PWR",
"brief": "Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
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"component": {
"mpn": "CDCLVC1106PWR",
"manufacturer": "Texas Instruments",
"package": "TSSOP-14",
"pin_count": 14,
"category": "Clock/Timing",
"subcategory": "Clock Buffers, Drivers, Distributors",
"datasheet": "https://www.ti.com/lit/ds/symlink/cdclvc1106.pdf",
"parts": {
"symbol": "cdclvc1106pwr.kicad_sym",
"footprint": "cdclvc1106pwr.kicad_mod",
"model_3d": "cdclvc1106pwr-etched.glb",
"model_3d_plain": "cdclvc1106pwr.glb",
"model_3d_step": "cdclvc1106pwr-etched.step",
"model_3d_step_plain": "cdclvc1106pwr.step",
"lbr": "cdclvc1106pwr.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "CLKIN",
"type": "input",
"description": "LVCMOS reference clock input. Accepts DC to 250 MHz at VDD=3.3 V (DC to 180 MHz at VDD=2.5 V). Input threshold is VDD/2; minimum pulse width 1.8 ns (3.3 V) or 2.75 ns (2.5 V)."
},
{
"number": "2",
"name": "1G",
"type": "input",
"description": "Asynchronous output enable. When driven low, all Y outputs are forced to a static low state; when high, outputs follow CLKIN. LVCMOS-level input."
},
{
"number": "3",
"name": "Y0",
"type": "output",
"description": "LVCMOS clock output 0, buffered copy of CLKIN. Unused outputs can be left floating."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Device ground. Tie to the board ground plane; all GND pins must be connected."
},
{
"number": "5",
"name": "VDD",
"type": "power_in",
"description": "2.5-V or 3.3-V device supply (3.0-3.6 V for 3.3-V mode, 2.3-2.7 V for 2.5-V mode). All VDD pins must be tied together and decoupled locally."
},
{
"number": "6",
"name": "Y4",
"type": "output",
"description": "LVCMOS clock output 4, buffered copy of CLKIN. Unused outputs can be left floating."
},
{
"number": "7",
"name": "GND",
"type": "power_in",
"description": "Device ground. Tie to the board ground plane; all GND pins must be connected."
},
{
"number": "8",
"name": "VDD",
"type": "power_in",
"description": "2.5-V or 3.3-V device supply. All VDD pins must be tied together and locally bypassed."
},
{
"number": "9",
"name": "Y5",
"type": "output",
"description": "LVCMOS clock output 5, buffered copy of CLKIN. Unused outputs can be left floating."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Device ground. Tie to the board ground plane; all GND pins must be connected."
},
{
"number": "11",
"name": "Y2",
"type": "output",
"description": "LVCMOS clock output 2, buffered copy of CLKIN. Unused outputs can be left floating."
},
{
"number": "12",
"name": "VDD",
"type": "power_in",
"description": "2.5-V or 3.3-V device supply. All VDD pins must be tied together and locally bypassed."
},
{
"number": "13",
"name": "Y3",
"type": "output",
"description": "LVCMOS clock output 3, buffered copy of CLKIN. Unused outputs can be left floating."
},
{
"number": "14",
"name": "Y1",
"type": "output",
"description": "LVCMOS clock output 1, buffered copy of CLKIN. Unused outputs can be left floating."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/cdclvc1106.pdf",
"pages": 37,
"sha256": "7b5ccb44b8bc0016",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 14,
"described": 14,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cdclvc1106pwr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
5,
1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cdclvc1106pwr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
5,
1
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "0a006be70ce9a07d6bba396d19bf5c3f67c38c102bfda4e6393f32bcf0f6a5a3",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "TSSOP-14",
"Category": "Clock/Timing",
"Pins": "14"
}
},
"variants": [
{
"mpn": "CDCLVC1106PWR",
"kind": "packaging"
}
],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"cdclvc1106pwr"
],
"discovery_pitch": "CDCLVC1106PWR (Texas Instruments) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cdclvc1106pwr.kicad_sym",
"cdclvc1106pwr.kicad_mod",
"cdclvc1106pwr.glb",
"cdclvc1106pwr.step",
"cdclvc1106pwr.lbr",
"docs/hero.png",
"docs/cdclvc1106pwr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"updated_at": "2026-09-24T18:58:41.504Z"
}