component

CDCLVC1106PWR

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cdclvc1106pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cdclvc1106pwr: viewers · Ray
cdclvc1106pwr-etched.fit.json cdclvc1106pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdclvc1106pwr-etched.glb cdclvc1106pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdclvc1106pwr-etched.step cdclvc1106pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdclvc1106pwr.glb Publish 0.1.0 · Ray
cdclvc1106pwr.kicad_mod Publish 0.1.0 · Ray
cdclvc1106pwr.kicad_sym Publish 0.1.0 · Ray
cdclvc1106pwr.lbr Publish 0.1.0 · Ray
cdclvc1106pwr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json cdclvc1106pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cdclvc1106pwr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CDCLVC1106PWR

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-14

CDCLVC1106PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input LVCMOS reference clock input. Accepts DC to 250 MHz at VDD=3.3 V (DC to 180 MHz at VDD=2.5 V). Input threshold is VDD/2; minimum pulse width 1.8 ns (3.3 V) or 2.75 ns (2.5 V).
2 1G input Asynchronous output enable. When driven low, all Y outputs are forced to a static low state; when high, outputs follow CLKIN. LVCMOS-level input.
3 Y0 output LVCMOS clock output 0, buffered copy of CLKIN. Unused outputs can be left floating.
4 GND power_in Device ground. Tie to the board ground plane; all GND pins must be connected.
5 VDD power_in 2.5-V or 3.3-V device supply (3.0-3.6 V for 3.3-V mode, 2.3-2.7 V for 2.5-V mode). All VDD pins must be tied together and decoupled locally.
6 Y4 output LVCMOS clock output 4, buffered copy of CLKIN. Unused outputs can be left floating.
7 GND power_in Device ground. Tie to the board ground plane; all GND pins must be connected.
8 VDD power_in 2.5-V or 3.3-V device supply. All VDD pins must be tied together and locally bypassed.
9 Y5 output LVCMOS clock output 5, buffered copy of CLKIN. Unused outputs can be left floating.
10 GND power_in Device ground. Tie to the board ground plane; all GND pins must be connected.
11 Y2 output LVCMOS clock output 2, buffered copy of CLKIN. Unused outputs can be left floating.
12 VDD power_in 2.5-V or 3.3-V device supply. All VDD pins must be tied together and locally bypassed.
13 Y3 output LVCMOS clock output 3, buffered copy of CLKIN. Unused outputs can be left floating.
14 Y1 output LVCMOS clock output 1, buffered copy of CLKIN. Unused outputs can be left floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Clock/Timing
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CDCLVC1106PWR

CAD (KiCad official)

  • Symbol: CDCLVC1106PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cdclvc1106pwr-etched.step / cdclvc1106pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvc1106pwr.step / cdclvc1106pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 7b5ccb44b8bc0016, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF