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CDCI6214RGET

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdci6214rgetfactory-2.0.0extractor-text

Verified CDCI6214RGET

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCI6214RGET · VQFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 104-page datasheet
  • ✓distributor: lcsc C2651236, digikey 296-47627-2-ND, mouser 595-CDCI6214RGET
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sxuo7p0t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdci6214rget.kicad_sym✓ cdci6214rget.kicad_mod✓ cdci6214rget.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

CDCI6214RGET

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-24-EP(4x4)

CDCI6214RGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XOUT/FB_P bidirectional Crystal driver output, LVCMOS input, or differential positive reference (FB_P) for the PLL, with the crystal path supporting 8 MHz to 50 MHz.
2 XIN/FB_N input Crystal input or differential negative reference (FB_N) for the PLL, with the crystal path supporting 8 MHz to 50 MHz.
3 VDDREF power_in Power supply for the input path, digital core and EEPROM, which must be within 1.71 V to 3.465 V and must be powered from the same supply as VDDVCO.
4 REFSEL input Manual reference selection MUX for the PLL with internal pullup RPU = 50 kΩ and pulldown RPD = 50 kΩ.
5 REFP input Differential positive reference input for the PLL.
6 REFN input Differential negative reference input for the PLL.
7 Y0 output Output 0 pin, with the output supply limited to 1.71 V to 3.465 V on the VDDO supplies.
8 RESETN/SYNC input Chip reset (active low) or, alternatively, output divider synchronization, with internal pullup RPU = 50 kΩ.
9 Y4N output Output 4 negative pin of the differential output pair.
10 Y4P output Output 4 positive pin of the differential output pair.
11 OE/GPIO4 bidirectional Global output enable (default) or programmable GPIO, with internal pullup RPU = 50 kΩ.
12 SCL/GPIO3 bidirectional Serial interface clock (default, I2C compatible up to 400 kHz) or programmable GPIO.
13 Y3N output Output 3 negative pin of the differential output pair.
14 Y3P output Output 3 positive pin of the differential output pair.
15 VDDO34 power_in Power supply for outputs 3 and 4, within 1.71 V to 3.465 V.
16 VDDO12 power_in Power supply for outputs 1 and 2, within 1.71 V to 3.465 V.
17 Y2N output Output 2 negative pin of the differential output pair.
18 Y2P output Output 2 positive pin of the differential output pair.
19 SDA/GPIO2 bidirectional Serial interface data (default, I2C compatible up to 400 kHz) or programmable GPIO.
20 STATUS/GPIO1 bidirectional Status output (default) or programmable GPIO, with internal pullup RPU = 50 kΩ.
21 Y1N output Output 1 negative pin of the differential output pair.
22 Y1P output Output 1 positive pin of the differential output pair.
23 EEPROMSEL input EEPROM page mode select, low loads page 0 and high loads page 1, with RPU = 50 kΩ and RPD = 50 kΩ.
24 VDDVCO power_in Power supply for the VCO and PLL, which must be powered from the same supply as VDDREF and within 1.71 V to 3.465 V.
25 GND power_in Ground connection on the exposed thermal pad, which should be connected with multiple vias to a solid GND plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category RTC/Clock Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage -0.3 3.65 V VDDREF, VDDVCO, VDDO12, VDDO34; over operating free-air temperature range 5
Input voltage -0.3 V XIN/FB_P, XOUT/FB_N, REFP, REFN; max VDDREF + 0.3 V 5
Output voltage -0.3 V Y0, Y1P, Y1N, Y2P, Y2N, Y3P, Y3N, Y4P, Y4N; max VDDO_x + 0.3 V 5
Junction temperature TJ 125 ºC 5
Storage temperature Tstg 150 ºC 5
Core supply voltage VDDREF, VDDVCO 1.71 3.465 V Core supply voltage 5
Output supply voltage VDDO1 1.71 3.465 V Output supply voltage 5
Ambient temperature TA -40 85 ºC 5
Junction-to-ambient thermal resistance RθJA 39.5 °C/W RGE (VQFN) 24 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 29.5 °C/W RGE (VQFN) 24 pins 5
Junction-to-board thermal resistance RθJB 16.9 °C/W RGE (VQFN) 24 pins 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.6 °C/W RGE (VQFN) 24 pins 5
Junction-to-top characterization parameter ψJT 0.4 °C/W RGE (VQFN) 24 pins 5
Junction-to-board characterization parameter ψJB 16.8 °C/W RGE (VQFN) 24 pins 5
Reference frequency fIN_Ref 1 250 MHz 6
Differential input voltage swing, peak-to-peak VIN_DIFF 0.5 1.6 V VDDREF = 2.5 V or 3.3 V, AC-coupled differential input buffer 6
Differential input voltage swing, peak-to-peak VIN_DIFF 0.5 1 V VDDREF = 1.8 V, AC-coupled differential input buffer 6
Input duty cycle IDC 40 60 % 6
Crystal frequency fIN_Xtal 8 50 MHz Fundamental mode 6
Crystal equivalent series resistance ZESR 30 100 Ω A supported crystal is within 6
Crystal load capacitance CL 5 8 pF Using on-chip load capacitance. A supported crystal is within. 6
Crystal tolerated drive power PXTAL 100 uW A supported crystal tolerates up to 6
On-chip load capacitance CXIN_LOAD 3 9.1 pF Programmable in typical 200-fF steps at room temp 6
Phase detector frequency fPFD 1 100 MHz 7
Voltage-controlled oscillator frequency fVCO 2400 2800 MHz 7
Configurable closed-loop PLL bandwidth fBW 100 3000 kHz REF = 25 MHz 7
Clock distribution frequency fCLKDIST 400 700 MHz 7
Output frequency fO_LVCMOS 0.1 350 MHz VDDO_x = 2.5 V or 3.3 V, normal drive 8
Output frequency fO_LVCMOS 0.1 250 MHz VDDO_x = 1.8 V, normal drive 8
Output frequency fO_HCSL 0.1 350 MHz 9
Output common mode VCM_HCSL 0.2 0.34 0.55 V 9
Differential output voltage VOD 0.4 1 V fO_HCSL = 100 MHz 9
Absolute crossing point VCROSS 250 550 mV Rp = 49.9 Ω ±5%, fO_HCSL = 100 MHz 9
Output duty cycle ODC 45 55 % Not in PLL bypass mode 9
Parallel termination RP 45 55 Ω Rp = 49.9 Ω ±5% required 9
Output common mode VCM 1.125 1.2 1.375 V VDDO_X = 2.5 V, 3.3 V, chx_lvds_cmtrim_inc = 2 9
Output common mode VCM 0.8 0.9 1 V VDDO_X = 1.8 V, chx_lvds_cmtrim_inc = 2 9
Differential output voltage LVDS VOD 0.25 0.3 0.45 V 9
Differential output voltage LVDS-like VOD 0.45 V Programmable differential AC-coupled output 9
EEPROM programming cycles nEEcyc 10 10000 cycles each word 6
Initialization time tINIT 5 ms Initialization time from POR to device releasing PLL outputs 10
Power supply ramp tVDD 50 2000 µs Timing requirement for any VDD pin while RESETN = LOW 10
Typical current IDD_TYP 83 mA 4x 156.25-MHz LVDS case using crystal input and doubler 12
VCO and PLL current IDD_VCO 13 mA fVCO = 2500 MHz, PSFB = PSA = 4 and PSB = off 11
Output channel current IDD_OUT 10 mA Activated output channel, 1x LVDS 156.25 MHz 11
SCL clock frequency fSCL 100 kHz Standard 11
SCL clock frequency fSCL 400 kHz Fast-mode 11
Propagation delay tPD_ZDM -600 600 ps REF = 67 MHz, VCO = 2680 MHz, external ZDM, LVCMOS 10
Skew between HCSL tSK_HCSL 140 ps Y[4:1] = HCSL, fOY[4:1] = 100 MHz 10
Low-level output voltage VOL 0.4 V At 3-mA sink current, VDDREF = 3.3 V, 5% 11
Low-level output current IOL 3 mA VOL = 0.4 V 11
Input capacitance GPIO CIN_GPIO 10 pF 6
Pullup resistance RPU 77 kΩ Pin 11, 20 7
Rise/fall time tRJ_CL 500 750 fs RMS phase jitter int. range 10 kHz to 20 MHz, XIN = Crystal 25 MHz, Yx = 156.25 MHz LVDS 8

CAD (KiCad official)

  • Symbol: CDCI6214RGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: cdci6214rget-etched.step / cdci6214rget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdci6214rget.step / cdci6214rget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (104 pp, sha256 393f17c509d0fd01, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF