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CDCF5801ADBQR
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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, SSOP-24-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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"name": "VDDREF",
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"description": "Reference voltage for REFCLK; it may be set to any value between 1.2 V and VDD and directly sets the REFCLK input trigger voltage."
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{
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"type": "input",
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"number": "7",
"name": "DLYCTRL",
"type": "input",
"description": "Each rising edge delays or advances CLKOUT/CLKOUTB by 1/768 of the CLKOUT period (1.3 mUI); allowable frequency up to 240 MHz with duty cycle of 25% to 75%."
},
{
"number": "8",
"name": "GNDPA",
"type": "power_in",
"description": "Ground for the phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB and PWRDNB."
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{
"number": "9",
"name": "VDDPA",
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"description": "Reference voltage for inputs LEADLAG and DLYCTRL, with an input reference voltage of 1.2 V to VDD."
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{
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"name": "STOPB",
"type": "input",
"description": "Active-low output disabler: when 0, CLKOUT and CLKOUTB go to a dc value per Table 2 while the PLL and phase aligner keep running; 1 is normal operation."
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{
"number": "12",
"name": "PWRDNB",
"type": "input",
"description": "Active-low power-down: when 0 the IC is in power-down and CLKOUT/CLKOUTB go low; 1 is normal operation."
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{
"number": "13",
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"description": "Post-divider control; together with P1 it selects the post divider (P[1:2] = 11 div2, 10 div4, 01 div8) per Table 1."
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{
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{
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"type": "output",
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{
"number": "21",
"name": "GNDO",
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{
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{
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{
"number": "24",
"name": "P0",
"type": "input",
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}
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{
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"name": "High-level output current",
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"name": "High-level output current",
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