CDCF5801ADBQR

{
  "slug": "cdcf5801adbqr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Generators / Frequency Synthesizers / PLL, SSOP-24-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "rtc-clock chip",
    "cdcf5801adbqr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
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    "cdcf5801adbqr.kicad_mod",
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    "cdcf5801adbqr.step",
    "cdcf5801adbqr.lbr",
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    "docs/cdcf5801adbqr-datasheet.pdf",
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  "component": {
    "mpn": "CDCF5801ADBQR",
    "manufacturer": "Texas Instruments",
    "package": "SSOP-24-150mil",
    "pin_count": 24,
    "category": "RTC/Clock Chip",
    "subcategory": "Clock Generators / Frequency Synthesizers / PLL",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cdcf5801a.pdf",
    "parts": {
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      "footprint": "cdcf5801adbqr.kicad_mod",
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      "model_3d_step_plain": "cdcf5801adbqr.step",
      "lbr": "cdcf5801adbqr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2878917",
      "digikey": "296-38077-2-ND",
      "mouser": "595-CDCF5801ADBQR"
    },
    "distributor_check": {
      "checked_at": "2026-11-06T01:20:22Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-38077-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-CDCF5801ADBQR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDDREF",
        "type": "power_in",
        "description": "Reference voltage for REFCLK; it may be set to any value between 1.2 V and VDD and directly sets the REFCLK input trigger voltage."
      },
      {
        "number": "2",
        "name": "REFCLK",
        "type": "input",
        "description": "Single-ended reference input clock with an input frequency of 12.5 MHz to 240 MHz and an input duty cycle of 40% to 60%."
      },
      {
        "number": "3",
        "name": "VDDP",
        "type": "power_in",
        "description": "VDD for the PLL and input buffer, specified at 3 V minimum, 3.3 V typical and 3.6 V maximum."
      },
      {
        "number": "4",
        "name": "GNDP",
        "type": "power_in",
        "description": "Ground for the PLL."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Ground for VDDREF and VDDPD."
      },
      {
        "number": "6",
        "name": "LEADLAG",
        "type": "input",
        "description": "Controls whether CLKOUT/CLKOUTB is delayed or advanced relative to REFCLK; allowable frequency up to 280 MHz with duty cycle of 25% to 75%."
      },
      {
        "number": "7",
        "name": "DLYCTRL",
        "type": "input",
        "description": "Each rising edge delays or advances CLKOUT/CLKOUTB by 1/768 of the CLKOUT period (1.3 mUI); allowable frequency up to 240 MHz with duty cycle of 25% to 75%."
      },
      {
        "number": "8",
        "name": "GNDPA",
        "type": "power_in",
        "description": "Ground for the phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB and PWRDNB."
      },
      {
        "number": "9",
        "name": "VDDPA",
        "type": "power_in",
        "description": "VDD for the phase aligner, digital logic, and inputs P[0:2], MULT[0:1] and STOPB."
      },
      {
        "number": "10",
        "name": "VDDPD",
        "type": "power_in",
        "description": "Reference voltage for inputs LEADLAG and DLYCTRL, with an input reference voltage of 1.2 V to VDD."
      },
      {
        "number": "11",
        "name": "STOPB",
        "type": "input",
        "description": "Active-low output disabler: when 0, CLKOUT and CLKOUTB go to a dc value per Table 2 while the PLL and phase aligner keep running; 1 is normal operation."
      },
      {
        "number": "12",
        "name": "PWRDNB",
        "type": "input",
        "description": "Active-low power-down: when 0 the IC is in power-down and CLKOUT/CLKOUTB go low; 1 is normal operation."
      },
      {
        "number": "13",
        "name": "P2",
        "type": "input",
        "description": "Post-divider control; together with P1 it selects the post divider (P[1:2] = 11 div2, 10 div4, 01 div8) per Table 1."
      },
      {
        "number": "14",
        "name": "MULT1",
        "type": "input",
        "description": "PLL multiplication factor select, used with MULT0; the terminal table lists MULT[0:1] = 00 as x4, 01 as x2, 11 as x8 and 10 as x16."
      },
      {
        "number": "15",
        "name": "MULT0",
        "type": "input",
        "description": "PLL multiplication factor select, used with MULT1 per Table 1 of the datasheet."
      },
      {
        "number": "16",
        "name": "VDDO",
        "type": "power_in",
        "description": "VDD for the output pins (CLKOUT, CLKOUTB) and the power-down circuit."
      },
      {
        "number": "17",
        "name": "GNDO",
        "type": "power_in",
        "description": "Ground for the output pins CLKOUT and CLKOUTB."
      },
      {
        "number": "18",
        "name": "CLKOUTB",
        "type": "output",
        "description": "Complementary low-noise CMOS output clock, with output frequency range of 25 MHz to 280 MHz."
      },
      {
        "number": "19",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected; leave floating or tie to GND."
      },
      {
        "number": "20",
        "name": "CLKOUT",
        "type": "output",
        "description": "Low-noise CMOS output clock, with output frequency range of 25 MHz to 280 MHz."
      },
      {
        "number": "21",
        "name": "GNDO",
        "type": "power_in",
        "description": "Ground for the output pins CLKOUT and CLKOUTB."
      },
      {
        "number": "22",
        "name": "VDDO",
        "type": "power_in",
        "description": "VDD for the output pins CLKOUT and CLKOUTB and the power-down circuit."
      },
      {
        "number": "23",
        "name": "P1",
        "type": "input",
        "description": "Post-divider control; together with P2 it selects the post divider (P[1:2] = 11 div2, 10 div4, 01 div8) per Table 1."
      },
      {
        "number": "24",
        "name": "P0",
        "type": "input",
        "description": "Mode control: 0 selects normal operation and 1 selects high-Z outputs and other special settings."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package variant: the datasheet prints the package as DBQ (SSOP, 24 pins) and the ordering table conf; Pin numbers for CLKOUT and CLKOUTB were garbled in the text extraction ('2018'). They were read as C; The datasheet is internally inconsistent on the MULT multiplication ratios. The terminal table gives",
          "2/24 pins cited to the wrong page (name found elsewhere): ['18:CLKOUTB@p4', '20:CLKOUT@p4']"
        ],
        "pages_sent": 20,
        "cost_usd": 0.0899,
        "at": "2026-11-06T01:19:37"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cdcf5801a.pdf",
        "pages": 20,
        "sha256": "680cbe8e952bcb05",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 24,
        "described": 24,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "seat": "z = 0",
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        "checked": "2026-11-06",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
        "file": "cdcf5801adbqr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "b271162f9cd999b6879a6c3e5f1ddba0e7c06a41373a25564eab50d369fd52c9",
        "checked": "2026-11-06",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "DBQ",
      "E1": {
        "nom_mm": 3.9,
        "range_mm": null
      },
      "E": {
        "nom_mm": 6.0,
        "range_mm": null
      },
      "e": {
        "nom_mm": 0.635,
        "range_mm": null
      },
      "source": "TI package designator DBQ (no drawing in the datasheet)",
      "model_check": {
        "file": "cdcf5801adbqr.step",
        "verdict": "SKIP",
        "reasons": [
          "the datasheet dimensions give no height or body size to compare"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}