# CDCF5801ADBQR

**Texas Instruments** · Clock Generators / Frequency Synthesizers / PLL · SSOP-24-150mil

CDCF5801ADBQR from Texas Instruments, in a SSOP-24-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDREF | power_in | Reference voltage for REFCLK; it may be set to any value between 1.2 V and VDD and directly sets the REFCLK input trigger voltage. |
| 2 | REFCLK | input | Single-ended reference input clock with an input frequency of 12.5 MHz to 240 MHz and an input duty cycle of 40% to 60%. |
| 3 | VDDP | power_in | VDD for the PLL and input buffer, specified at 3 V minimum, 3.3 V typical and 3.6 V maximum. |
| 4 | GNDP | power_in | Ground for the PLL. |
| 5 | GND | power_in | Ground for VDDREF and VDDPD. |
| 6 | LEADLAG | input | Controls whether CLKOUT/CLKOUTB is delayed or advanced relative to REFCLK; allowable frequency up to 280 MHz with duty cycle of 25% to 75%. |
| 7 | DLYCTRL | input | Each rising edge delays or advances CLKOUT/CLKOUTB by 1/768 of the CLKOUT period (1.3 mUI); allowable frequency up to 240 MHz with duty cycle of 25% to 75%. |
| 8 | GNDPA | power_in | Ground for the phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB and PWRDNB. |
| 9 | VDDPA | power_in | VDD for the phase aligner, digital logic, and inputs P[0:2], MULT[0:1] and STOPB. |
| 10 | VDDPD | power_in | Reference voltage for inputs LEADLAG and DLYCTRL, with an input reference voltage of 1.2 V to VDD. |
| 11 | STOPB | input | Active-low output disabler: when 0, CLKOUT and CLKOUTB go to a dc value per Table 2 while the PLL and phase aligner keep running; 1 is normal operation. |
| 12 | PWRDNB | input | Active-low power-down: when 0 the IC is in power-down and CLKOUT/CLKOUTB go low; 1 is normal operation. |
| 13 | P2 | input | Post-divider control; together with P1 it selects the post divider (P[1:2] = 11 div2, 10 div4, 01 div8) per Table 1. |
| 14 | MULT1 | input | PLL multiplication factor select, used with MULT0; the terminal table lists MULT[0:1] = 00 as x4, 01 as x2, 11 as x8 and 10 as x16. |
| 15 | MULT0 | input | PLL multiplication factor select, used with MULT1 per Table 1 of the datasheet. |
| 16 | VDDO | power_in | VDD for the output pins (CLKOUT, CLKOUTB) and the power-down circuit. |
| 17 | GNDO | power_in | Ground for the output pins CLKOUT and CLKOUTB. |
| 18 | CLKOUTB | output | Complementary low-noise CMOS output clock, with output frequency range of 25 MHz to 280 MHz. |
| 19 | NC | unconnected | Not connected; leave floating or tie to GND. |
| 20 | CLKOUT | output | Low-noise CMOS output clock, with output frequency range of 25 MHz to 280 MHz. |
| 21 | GNDO | power_in | Ground for the output pins CLKOUT and CLKOUTB. |
| 22 | VDDO | power_in | VDD for the output pins CLKOUT and CLKOUTB and the power-down circuit. |
| 23 | P1 | input | Post-divider control; together with P2 it selects the post divider (P[1:2] = 11 div2, 10 div4, 01 div8) per Table 1. |
| 24 | P0 | input | Mode control: 0 selects normal operation and 1 selects high-Z outputs and other special settings. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-24-150mil |
| Category | RTC/Clock Chip |
| Pins | 24 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDDP, VDDPA, VDDO) | VDDP, VDDPA, VDDO | 3 | 3.3 | 3.6 | V |  | 6 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 6 |
| High-level output current | IOH |  |  | -16 | mA |  | 6 |
| Low-level output current | IOL |  |  | 16 | mA |  | 6 |
| Input duty cycle on REFCLK |  | 40 |  | 60 | % |  | 6 |
| Input frequency on REFCLK |  | 12.5 |  | 240 | MHz |  | 6 |
| Output frequency on CLKOUT and CLKOUTB |  | 25 |  | 280 | MHz |  | 6 |
| Allowable frequency on DLYCTRL |  |  |  | 240 | MHz |  | 6 |
| Allowable frequency on LEADLAG |  |  |  | 280 | MHz |  | 7 |
| Allowable duty cycle on DLYCTRL and LEADLAG pins |  | 25 |  | 75 | % |  | 7 |
| Input slew rate | SR | 1 |  | 4 | V/ns |  | 6 |
| Input frequency of modulation (if driven by SSC CLKIN) | Fmod |  |  | 33 | kHz | if driven by SSC CLKIN | 6 |
| Modulation index, nonlinear |  | 0.5 |  | 0.6 | % | maximum | 6 |
| Supply voltage range | VDDx | -0.5 |  | 4 | V |  | 6 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 6 |
| Lead temperature |  |  |  | 260 | °C | 1,6 mm (1/16 inch) from case for 10 seconds | 6 |
| Power rating |  |  |  | 830 | mW | TA ≤ 25°C, DBQ | 6 |
| VO(STOP) Output voltage during Clkstop mode | VO(STOP) | 1.1 |  | 2 | V | See Figure 1 | 7 |
| Output voltage swing (VOH - VOL) | VO | 1.7 |  | 2.9 | V | See Figure 1 | 7 |
| Input clamp voltage | VIK |  |  | -1.2 | V | VDD = 3 V, II = -18 mA | 7 |
| High-level output voltage | VOH | 2 | 2.5 |  | V | VDD = 3 to 3.6 V, See Figure 1 | 7 |
| High-level output voltage | VOH | 2.2 |  |  | V | VDD = 3 V, IOH = -16 mA | 7 |
| Low-level output voltage | VOL |  | 0.4 | 0.6 | V | VDD = 3 to 3.6 V, See Figure 1 | 7 |
| Low-level output voltage | VOL |  |  | 0.5 | V | VDD = 3 V, IOH = 16 mA | 7 |
| High-level output current | IOH | -32 | -52 |  | mA | VDD = 3.135 V, VO = 1 V | 7 |
| High-level output current | IOH |  | -51 |  | mA | VDD = 3.3 V, VO = 1.65 V | 7 |
| High-level output current | IOH | -14.5 | -21 |  | mA | VDD = 3.465 V, VO = 3.135 V | 7 |
| Low-level output current | IOL | 43 | 61.5 |  | mA | VDD = 3.135 V, VO = 1.95 V | 7 |
| Low-level output current | IOL |  | 65 |  | mA | VDD = 3.3 V, VO = 1.65 V | 7 |
| Low-level output current | IOL | 25.5 | 40 |  | mA | VDD = 3.465 V, VO = 0.4 V | 7 |
| High-impedance-state output current | IOZ | -10 |  | 10 | µA | P0 = 1, P1 = P2 = 0 | 7 |
| High-impedance-state output current during Clk Stop | IOZ(STOP) | -100 |  | 100 | µA | Stop = 0, VO = GND or VDD | 7 |
| High-impedance-state output current in power-down state | IOZ(PD) | -10 |  | 100 | µA | PWRDNB = 0, VO = GND or VDD | 7 |
| High-level input current | IIH |  |  | 10 | µA | REFCLK; STOPB; PWRDNB; P[0:2]; MULT[0:1]; VDD = 3.6 V, VI = VDD | 7 |
| Low-level input current | IIL | -10 |  |  | µA | DLYCTRL; LEADLAG; VDD = 3.6 V, VI = 0 | 7 |
| Output high state impedance (single ended) | ZO | 15 | 35 | 50 | Ω | RI at IO -14.5 mA to -16.5 mA | 7 |
| Output low state impedance (single ended) | ZO | 10 | 17 | 35 | Ω | RI at IO 14.5 mA to 16.5 mA | 7 |
| Reference current VDDREF; VDDPD | IREF |  |  | 50 | µA | PWRDNB = 0, VDD = 3.6 V | 7 |
| Reference current VDDREF; VDDPD | IREF |  |  | 0.5 | mA | PWRDNB = 1, VDD = 3.6 V | 7 |
| Supply current in power-down state | IDD(PD) |  |  | 4 | mA | REFCLK = 0 MHz to 280 MHz; PWRDNB = 0; STOPB = 1 | 7 |
| Supply current in CLK stop state | IDD(CLKSTOP) |  |  | 44 | mA | BUSCLK configured for 280 MHz | 7 |
| Supply current (normal operation mode) | IDD(NORMAL) |  |  | 75 | mA | BUSCLK 280 MHz, MULT[0:1] = 10; P[0:2] = 011; Load, See Figure 1 | 7 |
| Output duty cycle over 1000 cycles | t(DC) | 42 |  | 58 | % | See Figure 3 | 9 |
| Output rise and fall times (20%-80% of output voltage) | tr, tf | 150 | 250 | 350 | ps | See Figure 5 | 9 |
| Delay time, PWRDNB↑ to CLKOUT/CLKOUTB settled (power up) | t(powerup) |  |  | 3 | ms | Power down to Normal; See Figure 6 | 9 |
| MULT0 and MULT1 change to CLKOUT output resettled | t(MULT) |  |  | 1 | ms | Normal to Normal; See Figure 7 | 10 |
| STOPB↑ to CLKOUT glitch-free clock edges | t(CLKON) |  |  | 10 | ns | CLK stop to Normal; See Figure 8 | 10 |
| STOPB↑ to CLKOUT output settled within 50 ps of the phase before CLK stop | t(CLKSETL) |  |  | 20 | cycles | Normal; See Figure 8 | 10 |
| STOPB↓ to CLKOUT output disabled | t(CLKOFF) |  |  | 5 | ns | Normal to CLK stop; See Figure 8 | 10 |
| Delay time, PWRDNB↓ to device in power-down mode | t(powerdown) |  |  | 1 | ms | Normal to Power down; See Figure 6 | 10 |
| Maximum time in CLKSTOP (STOPB = 0) before reentering normal mode | t(STOP) |  |  | 100 | µs | STOPB Normal; See Figure 8 | 10 |
| Minimum time in normal mode (STOPB = 1) before reentering CLKSTOP | t(ON) | 100 |  |  | ms | Normal to CLK stop; See Figure 8 | 10 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 25 MHz / CLKOUT 25 MHz | t(jitter) |  | 20 | 48 | ps | REFCLK 25 MHz, CLKOUT 25 MHz, MULT[0:1] 11, P[0:2] 001 | 8 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 50 MHz / CLKOUT 50 MHz | t(jitter) |  | 7 | 15 | ps | REFCLK 50 MHz, CLKOUT 50 MHz, MULT[0:1] 11, P[0:2] 001 | 8 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 100 MHz / CLKOUT 100 MHz | t(jitter) |  | 5 | 14 | ps | REFCLK 100 MHz, CLKOUT 100 MHz, MULT[0:1] 00, P[0:2] 010; phase aligner running | 8 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 156 MHz / CLKOUT 156 MHz | t(jitter) |  | 4 | 8 | ps | REFCLK 156 MHz, CLKOUT 156 MHz, MULT[0:1] 00, P[0:2] 010 | 8 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 200 MHz / CLKOUT 200 MHz | t(jitter) |  | 8 | 15 | ps | REFCLK 200 MHz, CLKOUT 200 MHz, MULT[0:1] 01, P[0:2] 011 | 8 |
| Period rms (1-sigma jitter, full frequency band), REFCLK 25 MHz / CLKOUT 200 MHz | t(jitter) |  | 4 | 11 | ps | REFCLK 25 MHz, CLKOUT 200 MHz, MULT[0:1] 10, P[0:2] 011 | 9 |
| Input capacitance | CI |  | 2 |  | pF | VI = VDD or GND | 7 |

## CAD (KiCad official)

- Symbol: `CDCF5801ADBQR`
- Footprint: `Package_SO:SSOP-24_3.9x8.7mm_P0.635mm`
- 3D model: SSOP-24-150mil (KiCad packages3D, STEP)
- 3D model files: `cdcf5801adbqr-etched.step` / `cdcf5801adbqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcf5801adbqr.step` / `cdcf5801adbqr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcf5801a.pdf) (20 pp, sha256 `680cbe8e952bcb05`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cdcf5801adbqr-datasheet.pdf)