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CDCEL824PWR

Public Made by Adom

by adom

Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16-175mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CDCEL824PWR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16-175mil

CDCEL824PWR from Texas Instruments, in a TSSOP-16-175mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Xin/CLK input Crystal oscillator input or LVCMOS clock input, selectable via the SDA/SCL bus; the LVCMOS clock input accepts up to 130 MHz and the crystal input range is 10 MHz to 30 MHz (fundamental mode).
2 S0 input User-programmable LVCMOS control input S0 with internal pullup; it is a control pin only and in default mode switches all outputs on or off.
3 VDD power_in 1.8-V device power supply, recommended operating range 1.7 V to 1.9 V.
4 VCtrl input VCXO control voltage input; leave open or pull up when not used, with a frequency control voltage range of 0 V to VDD.
5 GND power_in Ground reference for the device.
6 VDDOUT power_in 1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V.
7 Y3 output LVCMOS clock output Y3, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V.
8 Y4 output LVCMOS clock output Y4, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V.
9 VDDOUT power_in 1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V.
10 Y2 output LVCMOS clock output Y2, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V.
11 Y1 output LVCMOS clock output Y1, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V.
12 GND power_in Ground reference for the device.
13 DNC unconnected Reserved pin, do not connect.
14 SCL/S2 input Serial clock input (SCL, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S2 with internal pullup, with inputs up to 3.6 V.
15 SDA/S1 bidirectional Serial data input/output (SDA, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S1 with internal pullup, with inputs up to 3.6 V.
16 Xout output Crystal oscillator output; leave open or pull up when not used.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16-175mil
Category Clock/Timing
Pins 16

CAD (KiCad official)

  • Symbol: CDCEL824PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16-175mil (KiCad packages3D, STEP)
  • 3D model files: cdcel824pwr-etched.step / cdcel824pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcel824pwr.step / cdcel824pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 b27c2d3459f6b7d8, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF