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CDCEL824PWR
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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16-175mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CDCEL824PWR++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16-175mil++CDCEL824PWR from Texas Instruments, in a TSSOP-16-175mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Xin/CLK | input | Crystal oscillator input or LVCMOS clock input, selectable via the SDA/SCL bus; the LVCMOS clock input accepts up to 130 MHz and the crystal input range is 10 MHz to 30 MHz (fundamental mode). |+| 2 | S0 | input | User-programmable LVCMOS control input S0 with internal pullup; it is a control pin only and in default mode switches all outputs on or off. |+| 3 | VDD | power_in | 1.8-V device power supply, recommended operating range 1.7 V to 1.9 V. |+| 4 | VCtrl | input | VCXO control voltage input; leave open or pull up when not used, with a frequency control voltage range of 0 V to VDD. |+| 5 | GND | power_in | Ground reference for the device. |+| 6 | VDDOUT | power_in | 1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V. |+| 7 | Y3 | output | LVCMOS clock output Y3, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V. |+| 8 | Y4 | output | LVCMOS clock output Y4, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V. |+| 9 | VDDOUT | power_in | 1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V. |+| 10 | Y2 | output | LVCMOS clock output Y2, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V. |+| 11 | Y1 | output | LVCMOS clock output Y1, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V. |+| 12 | GND | power_in | Ground reference for the device. |+| 13 | DNC | unconnected | Reserved pin, do not connect. |+| 14 | SCL/S2 | input | Serial clock input (SCL, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S2 with internal pullup, with inputs up to 3.6 V. |+| 15 | SDA/S1 | bidirectional | Serial data input/output (SDA, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S1 with internal pullup, with inputs up to 3.6 V. |+| 16 | Xout | output | Crystal oscillator output; leave open or pull up when not used. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16-175mil |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CDCEL824PWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16-175mil (KiCad packages3D, STEP)+- 3D model files: `cdcel824pwr-etched.step` / `cdcel824pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcel824pwr.step` / `cdcel824pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcel824.pdf) (33 pp, sha256 `b27c2d3459f6b7d8`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcel824pwr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "cdcel824pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16-175mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdcel824pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcel824pwr.kicad_sym",+ "cdcel824pwr.kicad_mod",+ "cdcel824pwr.glb",+ "cdcel824pwr.step",+ "cdcel824pwr.lbr",+ "docs/hero.png",+ "docs/cdcel824pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdcel824pwr-hero.glb",+ "cdcel824pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCEL824PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16-175mil",+ "pin_count": 16,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cdcel824.pdf",+ "parts": {+ "symbol": "cdcel824pwr.kicad_sym",+ "footprint": "cdcel824pwr.kicad_mod",+ "model_3d": "cdcel824pwr-hero.glb",+ "model_3d_plain": "cdcel824pwr.glb",+ "model_3d_step": "cdcel824pwr-etched.step",+ "model_3d_step_plain": "cdcel824pwr.step",+ "lbr": "cdcel824pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2662631",+ "digikey": "296-43373-2-ND",+ "mouser": "595-CDCEL824PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:27:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-43373-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDCEL824PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "Xin/CLK",+ "type": "input",+ "description": "Crystal oscillator input or LVCMOS clock input, selectable via the SDA/SCL bus; the LVCMOS clock input accepts up to 130 MHz and the crystal input range is 10 MHz to 30 MHz (fundamental mode)."+ },+ {+ "number": "2",+ "name": "S0",+ "type": "input",+ "description": "User-programmable LVCMOS control input S0 with internal pullup; it is a control pin only and in default mode switches all outputs on or off."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "1.8-V device power supply, recommended operating range 1.7 V to 1.9 V."+ },+ {+ "number": "4",+ "name": "VCtrl",+ "type": "input",+ "description": "VCXO control voltage input; leave open or pull up when not used, with a frequency control voltage range of 0 V to VDD."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "6",+ "name": "VDDOUT",+ "type": "power_in",+ "description": "1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V."+ },+ {+ "number": "7",+ "name": "Y3",+ "type": "output",+ "description": "LVCMOS clock output Y3, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V."+ },+ {+ "number": "8",+ "name": "Y4",+ "type": "output",+ "description": "LVCMOS clock output Y4, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V."+ },+ {+ "number": "9",+ "name": "VDDOUT",+ "type": "power_in",+ "description": "1.8-V supply for all outputs, recommended operating range 1.7 V to 1.9 V."+ },+ {+ "number": "10",+ "name": "Y2",+ "type": "output",+ "description": "LVCMOS clock output Y2, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V."+ },+ {+ "number": "11",+ "name": "Y1",+ "type": "output",+ "description": "LVCMOS clock output Y1, driving up to 15 pF load with output current of ±8 mA at VDDOUT = 1.8 V."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "13",+ "name": "DNC",+ "type": "unconnected",+ "description": "Reserved pin, do not connect."+ },+ {+ "number": "14",+ "name": "SCL/S2",+ "type": "input",+ "description": "Serial clock input (SCL, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S2 with internal pullup, with inputs up to 3.6 V."+ },+ {+ "number": "15",+ "name": "SDA/S1",+ "type": "bidirectional",+ "description": "Serial data input/output (SDA, LVCMOS, internal pullup) in default configuration; can be reprogrammed as user-programmable control input S1 with internal pullup, with inputs up to 3.6 V."+ },+ {+ "number": "16",+ "name": "Xout",+ "type": "output",+ "description": "Crystal oscillator output; leave open or pull up when not used."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package conflict: the pin-configuration header on page 3 reads 'PW Package 20-Pin TSSOP', but the pi; Package hint 'TSSOP-16-175mil': the 175 mil width is not stated anywhere in the supplied text. The d; Pin 13 (DNC) is listed as 'O' in the source table; it was typed as 'unconnected' because the datashe"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0722,+ "at": "2026-10-07T22:27:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdcel824.pdf",+ "pages": 33,+ "sha256": "b27c2d3459f6b7d8",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcel824pwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcel824pwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4421192032704dc4ea18eda5f33c436edc2552bfe466c66aecfa7db8380ea3c1",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}