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CDCE937QPWRQ1

Public Made by Adom

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CDCE937QPWRQ1

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-20

CDCE937QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Xin/CLK input Crystal oscillator input or LVCMOS clock input (selected via the SDA/SCL bus), with crystal fundamental frequency 8 MHz to 32 MHz and clock input range 0 to 1.9 V.
2 S0 input User-programmable LVCMOS control input with an internal 500 kΩ pull-up resistor, with input voltage range 0 to 1.9 V; it is the only control pin that is never multiplexed with the serial interface.
3 VDD power_in 1.8 V device supply, with recommended range 1.7 V to 1.9 V.
4 VCtrl input VCXO control voltage input, to be left open or pulled up to about 500 kΩ when unused, with control voltage range 0 to VDD.
5 GND power_in Ground.
6 Vddout power_in Output supply for all Y outputs: 3.3 V or 2.5 V for CDCE937-Q1 (recommended range 2.3 V to 3.6 V), 1.8 V for CDCEL937-Q1 (1.7 V to 1.9 V).
7 Y4 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
8 Y5 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
9 GND power_in Ground.
10 Vddout power_in Output supply for all Y outputs: 3.3 V or 2.5 V for CDCE937-Q1 (recommended range 2.3 V to 3.6 V), 1.8 V for CDCEL937-Q1 (1.7 V to 1.9 V).
11 Y7 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
12 Y6 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
13 Vddout power_in Output supply for all Y outputs: 3.3 V or 2.5 V for CDCE937-Q1 (recommended range 2.3 V to 3.6 V), 1.8 V for CDCEL937-Q1 (1.7 V to 1.9 V).
14 Y3 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
15 Y2 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
16 GND power_in Ground.
17 Y1 output LVCMOS clock output, with output current limited to IOH/IOL of ±12 mA at 3.3 V, ±10 mA at 2.5 V, or ±8 mA at 1.8 V.
18 SCL/S2 input Serial clock input for the SDA/SCL bus (default function, 500 kΩ internal pull-up), or user-programmable LVCMOS control input S2 when SPICON is set in EEPROM; SDA/SCL inputs are rated up to 3.6 V.
19 SDA/S1 bidirectional Bidirectional serial data line for the SDA/SCL bus (default function, 500 kΩ internal pull-up), or user-programmable LVCMOS control input S1 when SPICON is set in EEPROM; SDA is rated up to 3.6 V.
20 Xout output Crystal oscillator output, to be left open or pulled up to about 500 kΩ when unused.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Clock/Timing
Pins 20

CAD (KiCad official)

  • Symbol: CDCE937QPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: cdce937qpwrq1-etched.step / cdce937qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce937qpwrq1.step / cdce937qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 f211c5dd15df35c8, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF