component
CDCDB803RSLR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "cdcdb803rslr",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"clock-timing",
"cdcdb803rslr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cdcdb803rslr.kicad_sym",
"cdcdb803rslr.kicad_mod",
"cdcdb803rslr.glb",
"cdcdb803rslr.step",
"cdcdb803rslr.lbr",
"docs/hero.png",
"docs/cdcdb803rslr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cdcdb803rslr-hero.glb",
"cdcdb803rslr-hero.overlay.json"
],
"component": {
"mpn": "CDCDB803RSLR",
"manufacturer": "Texas Instruments",
"package": "VQFN-48(6x6)",
"pin_count": 49,
"category": "Clock/Timing",
"subcategory": "Clock Buffers, Drivers, Distributors",
"datasheet": "https://www.ti.com/cn/lit/gpn/cdcdb803",
"parts": {
"symbol": "cdcdb803rslr.kicad_sym",
"footprint": "cdcdb803rslr.kicad_mod",
"model_3d": "cdcdb803rslr-hero.glb",
"model_3d_plain": "cdcdb803rslr.glb",
"model_3d_step": "cdcdb803rslr-etched.step",
"model_3d_step_plain": "cdcdb803rslr.step",
"lbr": "cdcdb803rslr.lbr"
},
"distributor_links": {
"lcsc": "C5215100",
"digikey": "296-CDCDB803RSLRTR-ND",
"mouser": "595-CDCDB803RSLR"
},
"distributor_check": {
"checked_at": "2026-10-08T03:20:03Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-CDCDB803RSLRTR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-CDCDB803RSLR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "CKPWRGD_PD#",
"type": "input",
"description": "Multi-function clock power-good/power-down input with internal 180-kΩ pulldown; after PWRGD is first asserted high, LOW puts all output channels in tri-state power-down and HIGH selects normal operation."
},
{
"number": "2",
"name": "VDDR",
"type": "power_in",
"description": "3.3-V power supply input for the input clock receiver (3 V to 3.6 V), to be decoupled with a 0.1-µF capacitor placed close to the pin."
},
{
"number": "3",
"name": "CLKIN_P",
"type": "input",
"description": "Positive LP-HCSL differential clock input, typically connected directly to the differential output of the clock source."
},
{
"number": "4",
"name": "CLKIN_N",
"type": "input",
"description": "Negative LP-HCSL differential clock input, typically connected directly to the differential output of the clock source."
},
{
"number": "5",
"name": "SADR0",
"type": "input",
"description": "SMBus address strap bit 0, a three-level input decoded together with pin 8, with internal 180-kΩ pullup/pulldown biasing to GND when no connect; high uses a 1 kΩ to 5 kΩ (5%) pullup to 3.3 V, low uses a 1 kΩ to 5 kΩ (5%) pulldown, and mid-level is left floating."
},
{
"number": "6",
"name": "SMBDAT",
"type": "bidirectional",
"description": "SMBus data pin, typically pulled up to 3.3 V with a pullup resistor greater than 8.5 kΩ."
},
{
"number": "7",
"name": "SMBCLK",
"type": "input",
"description": "SMBus clock pin, typically pulled up to 3.3 V with a pullup resistor greater than 8.5 kΩ."
},
{
"number": "8",
"name": "SADR1",
"type": "input",
"description": "SMBus address strap bit 1, a three-level input decoded together with SADR0, with internal 180-kΩ pullup/pulldown biasing to GND when no connect; high uses a 1 kΩ to 5 kΩ (5%) pullup to 3.3 V, low uses a 1 kΩ to 5 kΩ (5%) pulldown, and mid-level is left floating."
},
{
"number": "9",
"name": "NC",
"type": "unconnected",
"description": "No connect; do not connect to GND or VDD."
},
{
"number": "10",
"name": "NC",
"type": "unconnected",
"description": "No connect; do not connect to GND or VDD."
},
{
"number": "11",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "12",
"name": "OE0#",
"type": "input",
"description": "Active-low output enable for channel 0 with internal 180-kΩ pulldown; LOW enables output CK0 and HIGH disables it."
},
{
"number": "13",
"name": "CK0_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 0, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "14",
"name": "CK0_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 0, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "16",
"name": "CK1_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 1, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "17",
"name": "CK1_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 1, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "18",
"name": "OE1#",
"type": "input",
"description": "Active-low output enable for channel 1 with internal 180-kΩ pulldown; LOW enables output CK1 and HIGH disables it."
},
{
"number": "19",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "20",
"name": "NC",
"type": "unconnected",
"description": "No connect; do not connect to GND or VDD."
},
{
"number": "21",
"name": "CK2_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 2, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "22",
"name": "CK2_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 2, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "23",
"name": "OE2#",
"type": "input",
"description": "Active-low output enable for channel 2 with internal 180-kΩ pulldown; LOW enables output CK2 and HIGH disables it."
},
{
"number": "24",
"name": "OE3#",
"type": "input",
"description": "Active-low output enable for channel 3 with internal 180-kΩ pulldown; LOW enables output CK3 and HIGH disables it."
},
{
"number": "25",
"name": "CK3_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 3, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "26",
"name": "CK3_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 3, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "28",
"name": "CK4_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 4, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "29",
"name": "CK4_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 4, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "30",
"name": "OE4#",
"type": "input",
"description": "Active-low output enable for channel 4 with internal 180-kΩ pulldown; LOW enables output CK4 and HIGH disables it."
},
{
"number": "31",
"name": "OE5#",
"type": "input",
"description": "Active-low output enable for channel 5 with internal 180-kΩ pulldown; LOW enables output CK5 and HIGH disables it."
},
{
"number": "32",
"name": "CK5_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 5, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "33",
"name": "CK5_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 5, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "34",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "35",
"name": "CK6_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 6, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "36",
"name": "CK6_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 6, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "37",
"name": "OE6#",
"type": "input",
"description": "Active-low output enable for channel 6 with internal 180-kΩ pulldown; LOW enables output CK6 and HIGH disables it."
},
{
"number": "38",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "39",
"name": "CK7_P",
"type": "output",
"description": "Positive LP-HCSL differential clock output of channel 7, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "40",
"name": "CK7_N",
"type": "output",
"description": "Negative LP-HCSL differential clock output of channel 7, typically connected directly to a PCIe differential clock input; may be left unconnected if unused."
},
{
"number": "41",
"name": "OE7#",
"type": "input",
"description": "Active-low output enable for channel 7 with internal 180-kΩ pulldown; LOW enables output CK7 and HIGH disables it."
},
{
"number": "42",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "43",
"name": "NC",
"type": "unconnected",
"description": "No connect; do not connect to GND or VDD."
},
{
"number": "44",
"name": "VDD",
"type": "power_in",
"description": "3.3-V power supply for the output channels and core voltage (3 V to 3.6 V)."
},
{
"number": "45",
"name": "NC",
"type": "unconnected",
"description": "No connect; do not connect to GND or VDD."
},
{
"number": "46",
"name": "SMBWRTLOCK",
"type": "input",
"description": "Active-high SMBus write lock with internal 180-kΩ pulldown; when asserted, all SMBus writes are ignored while reads are unaffected."
},
{
"number": "47",
"name": "NC",
"type": "unconnected",
"description": "No connect; pin may be tied to GND, VDD, or any potential within the absolute maximum supply range."
},
{
"number": "48",
"name": "NC",
"type": "unconnected",
"description": "No connect; pin may be tied to GND, VDD, or any potential within the absolute maximum supply range."
},
{
"number": "49",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The GND exposed die attach pad (DAP) is listed in the datasheet pin table as 'GND DAP' with no print; The SADR1 description in the datasheet says it is decoded 'in conjunction with pin B4', which is a B; The datasheet pin table is from the RSL 48-pin VQFN top view. The orderable table lists CDCDB803RSLR",
"exposed pad 49 added from the footprint",
"dropped thermal pad ['EP'] absent from footprint"
],
"pages_sent": 15,
"cost_usd": 0.1201,
"at": "2026-10-08T03:19:33"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/cdcdb803",
"pages": 34,
"sha256": "bb59e9833746465d",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cdcdb803rslr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "24e962a676a03ddfe213c32517bfe7608eabfbf97da5f57fff82d57193c9df22",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cdcdb803rslr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "3d6070ed265e9fc12b12974dc0aab6afb14add6a325a991d79d2b002d2e76cf1",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}