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CDCDB803RSLR

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Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CDCDB803RSLR

Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-48(6x6)

CDCDB803RSLR from Texas Instruments, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CKPWRGD_PD# input Multi-function clock power-good/power-down input with internal 180-kΩ pulldown; after PWRGD is first asserted high, LOW puts all output channels in tri-state power-down and HIGH selects normal operation.
2 VDDR power_in 3.3-V power supply input for the input clock receiver (3 V to 3.6 V), to be decoupled with a 0.1-µF capacitor placed close to the pin.
3 CLKIN_P input Positive LP-HCSL differential clock input, typically connected directly to the differential output of the clock source.
4 CLKIN_N input Negative LP-HCSL differential clock input, typically connected directly to the differential output of the clock source.
5 SADR0 input SMBus address strap bit 0, a three-level input decoded together with pin 8, with internal 180-kΩ pullup/pulldown biasing to GND when no connect; high uses a 1 kΩ to 5 kΩ (5%) pullup to 3.3 V, low uses a 1 kΩ to 5 kΩ (5%) pulldown, and mid-level is left floating.
6 SMBDAT bidirectional SMBus data pin, typically pulled up to 3.3 V with a pullup resistor greater than 8.5 kΩ.
7 SMBCLK input SMBus clock pin, typically pulled up to 3.3 V with a pullup resistor greater than 8.5 kΩ.
8 SADR1 input SMBus address strap bit 1, a three-level input decoded together with SADR0, with internal 180-kΩ pullup/pulldown biasing to GND when no connect; high uses a 1 kΩ to 5 kΩ (5%) pullup to 3.3 V, low uses a 1 kΩ to 5 kΩ (5%) pulldown, and mid-level is left floating.
9 NC unconnected No connect; do not connect to GND or VDD.
10 NC unconnected No connect; do not connect to GND or VDD.
11 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
12 OE0# input Active-low output enable for channel 0 with internal 180-kΩ pulldown; LOW enables output CK0 and HIGH disables it.
13 CK0_P output Positive LP-HCSL differential clock output of channel 0, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
14 CK0_N output Negative LP-HCSL differential clock output of channel 0, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
15 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
16 CK1_P output Positive LP-HCSL differential clock output of channel 1, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
17 CK1_N output Negative LP-HCSL differential clock output of channel 1, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
18 OE1# input Active-low output enable for channel 1 with internal 180-kΩ pulldown; LOW enables output CK1 and HIGH disables it.
19 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
20 NC unconnected No connect; do not connect to GND or VDD.
21 CK2_P output Positive LP-HCSL differential clock output of channel 2, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
22 CK2_N output Negative LP-HCSL differential clock output of channel 2, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
23 OE2# input Active-low output enable for channel 2 with internal 180-kΩ pulldown; LOW enables output CK2 and HIGH disables it.
24 OE3# input Active-low output enable for channel 3 with internal 180-kΩ pulldown; LOW enables output CK3 and HIGH disables it.
25 CK3_P output Positive LP-HCSL differential clock output of channel 3, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
26 CK3_N output Negative LP-HCSL differential clock output of channel 3, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
27 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
28 CK4_P output Positive LP-HCSL differential clock output of channel 4, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
29 CK4_N output Negative LP-HCSL differential clock output of channel 4, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
30 OE4# input Active-low output enable for channel 4 with internal 180-kΩ pulldown; LOW enables output CK4 and HIGH disables it.
31 OE5# input Active-low output enable for channel 5 with internal 180-kΩ pulldown; LOW enables output CK5 and HIGH disables it.
32 CK5_P output Positive LP-HCSL differential clock output of channel 5, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
33 CK5_N output Negative LP-HCSL differential clock output of channel 5, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
34 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
35 CK6_P output Positive LP-HCSL differential clock output of channel 6, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
36 CK6_N output Negative LP-HCSL differential clock output of channel 6, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
37 OE6# input Active-low output enable for channel 6 with internal 180-kΩ pulldown; LOW enables output CK6 and HIGH disables it.
38 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
39 CK7_P output Positive LP-HCSL differential clock output of channel 7, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
40 CK7_N output Negative LP-HCSL differential clock output of channel 7, typically connected directly to a PCIe differential clock input; may be left unconnected if unused.
41 OE7# input Active-low output enable for channel 7 with internal 180-kΩ pulldown; LOW enables output CK7 and HIGH disables it.
42 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
43 NC unconnected No connect; do not connect to GND or VDD.
44 VDD power_in 3.3-V power supply for the output channels and core voltage (3 V to 3.6 V).
45 NC unconnected No connect; do not connect to GND or VDD.
46 SMBWRTLOCK input Active-high SMBus write lock with internal 180-kΩ pulldown; when asserted, all SMBus writes are ignored while reads are unaffected.
47 NC unconnected No connect; pin may be tied to GND, VDD, or any potential within the absolute maximum supply range.
48 NC unconnected No connect; pin may be tied to GND, VDD, or any potential within the absolute maximum supply range.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48(6x6)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: CDCDB803RSLR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm
  • 3D model: VQFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cdcdb803rslr-etched.step / cdcdb803rslr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcdb803rslr.step / cdcdb803rslr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 bb59e9833746465d, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF