component
CD74HCT597M96
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"manufacturer": "Texas Instruments",
"package": "SOIC-16",
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"subcategory": "Shift Registers",
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{
"number": "1",
"name": "D1",
"type": "input",
"description": "Parallel data input to storage flip-flop D1, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "2",
"name": "D2",
"type": "input",
"description": "Parallel data input to storage flip-flop D2, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "3",
"name": "D3",
"type": "input",
"description": "Parallel data input to storage flip-flop D3, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "4",
"name": "D4",
"type": "input",
"description": "Parallel data input to storage flip-flop D4, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "5",
"name": "D5",
"type": "input",
"description": "Parallel data input to storage flip-flop D5, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "6",
"name": "D6",
"type": "input",
"description": "Parallel data input to storage flip-flop D6, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "7",
"name": "D7",
"type": "input",
"description": "Parallel data input to storage flip-flop D7, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin for the device (supply range 4.5V to 5.5V for HCT types)."
},
{
"number": "9",
"name": "Q7",
"type": "output",
"description": "Serial data output from the last stage of the 8-bit shift register; standard outputs drive 10 LSTTL loads over temperature."
},
{
"number": "10",
"name": "MR",
"type": "input",
"description": "Active-low master reset that clears the shift register when low; MR unit load is 1.5 and HCT VIL max is 0.8V, VIH min 2V."
},
{
"number": "11",
"name": "SHCP",
"type": "input",
"description": "Shift register clock; data is shifted on the low-to-high transition when MR and PL are high; unit load is 1.5."
},
{
"number": "12",
"name": "STCP",
"type": "input",
"description": "Storage register clock; a low-to-high transition loads the Dn inputs into the input flip-flops; unit load is 1.5."
},
{
"number": "13",
"name": "PL",
"type": "input",
"description": "Active-low asynchronous parallel load; a low shifts parallel stored data into the shift register; unit load is 1.5."
},
{
"number": "14",
"name": "DS",
"type": "input",
"description": "Serial data input to the first shift register stage (Q0), shifted in on SHCP transitions when PL is high; DS unit load is 0.2."
},
{
"number": "15",
"name": "D0",
"type": "input",
"description": "Parallel data input to storage flip-flop D0, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply; HCT operating range is 4.5V to 5.5V."
}
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"extractor flagged: The extracted text lists pin numbers and pin names as separate, reordered columns in the pinout figu; The package is SOIC-16 (D). The ordering table and package materials list CD74HCT597M96 as a 16 Ld S; Pin types, descriptions and unit loads for D0 to D7, DS, PL, MR, STCP, SHCP are taken from the funct"
],
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"at": "2026-10-18T05:28:00"
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