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CD74HCT597M96

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Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74HCT597M96

Texas Instruments · Shift Registers · SOIC-16

CD74HCT597M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input to storage flip-flop D1, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
2 D2 input Parallel data input to storage flip-flop D2, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
3 D3 input Parallel data input to storage flip-flop D3, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
4 D4 input Parallel data input to storage flip-flop D4, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
5 D5 input Parallel data input to storage flip-flop D5, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
6 D6 input Parallel data input to storage flip-flop D6, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
7 D7 input Parallel data input to storage flip-flop D7, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
8 GND power_in Ground reference pin for the device (supply range 4.5V to 5.5V for HCT types).
9 Q7 output Serial data output from the last stage of the 8-bit shift register; standard outputs drive 10 LSTTL loads over temperature.
10 MR input Active-low master reset that clears the shift register when low; MR unit load is 1.5 and HCT VIL max is 0.8V, VIH min 2V.
11 SHCP input Shift register clock; data is shifted on the low-to-high transition when MR and PL are high; unit load is 1.5.
12 STCP input Storage register clock; a low-to-high transition loads the Dn inputs into the input flip-flops; unit load is 1.5.
13 PL input Active-low asynchronous parallel load; a low shifts parallel stored data into the shift register; unit load is 1.5.
14 DS input Serial data input to the first shift register stage (Q0), shifted in on SHCP transitions when PL is high; DS unit load is 0.2.
15 D0 input Parallel data input to storage flip-flop D0, loaded into the shift register asynchronously when PL is low; Dn unit load is 0.3 and HCT input thresholds are VIL 0.8V max and VIH 2V min.
16 VCC power_in Positive supply; HCT operating range is 4.5V to 5.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Level Input Voltage VIH 2 V VCC = 4.5 to 5.5 V; -55oC to 125oC 4
Low Level Input Voltage VIL 0.8 V VCC = 4.5 to 5.5 V; -55oC to 125oC 4
High Level Output Voltage, CMOS Loads VOH 4.4 V VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V; -55oC to 125oC 4
High Level Output Voltage, TTL Loads VOH 3.7 V IO = -4 mA; VCC = 4.5 V; -55oC to 125oC 4
Low Level Output Voltage, CMOS Loads VOL 0.1 V VI = VIH or VIL; IO = 0.02 mA; VCC = 4.5 V; -55oC to 125oC 4
Low Level Output Voltage, TTL Loads VOL 0.4 V IO = 4 mA; VCC = 4.5 V; -55oC to 125oC 4
Input Leakage Current II -1 1 µA VI = VCC and GND; IO = 0; VCC = 5.5 V; -55oC to 125oC 4
Quiescent Device Current ICC 160 µA VI = VCC or GND; IO = 0; VCC = 5.5 V; -55oC to 125oC 4
Additional Quiescent Device Current Per Input Pin: 1 Unit Load ΔICC 100 490 µA VI = VCC - 2.1 V; VCC = 4.5 to 5.5 V; typ at 25oC, max at -55oC to 125oC; see Note 2 4
Additional Quiescent Device Current Per Input Pin, dual-supply theoretical worst case ΔICC 1.8 mA Note 2: VI = 2.4 V, VCC = 5.5 V 4
SHCP Frequency fMAX 16 MHz VCC = 4.5 V; -55oC to 125oC 5
SHCP Pulse Width tW 30 ns VCC = 4.5 V; -55oC to 125oC 5
STCP Pulse Width tW 20 ns VCC = 4.5 V; -55oC to 125oC 5
MR Pulse Width tW 27 ns VCC = 4.5 V; -55oC to 125oC 5
PL Pulse Width tW 24 ns VCC = 4.5 V; -55oC to 125oC 5
STCP to SHCP Setup Time tSU 36 ns VCC = 4.5 V; -55oC to 125oC 5
DS to SHCP Setup Time / Dn to STCP Setup Time tH 15 ns VCC = 4.5 V; -55oC to 125oC 6
STCP to SHCP Hold Time tH 0 ns VCC = 4.5 V; -55oC to 125oC 6
DS to SHCP Hold Time / Dn to STCP Hold Time tH 3 ns VCC = 4.5 V; -55oC to 125oC 6
MR to SHCP Removal Time tREM 15 ns VCC = 4.5 V; -55oC to 125oC 6
Propagation Delay SHCP to Q7 tPLH, tPHL 57 ns CL = 50pF; VCC = 4.5 V; -55oC to 125oC 6
Propagation Delay PL to Q7 tPLH, tPHL 72 ns CL = 50pF; VCC = 4.5 V; -55oC to 125oC 6
Propagation Delay STCP to Q7 tPLH, tPHL 84 ns CL = 50pF; VCC = 4.5 V; -55oC to 125oC 6
Propagation Delay MR to Q7 tPLH, tPHL 66 ns CL = 50pF; VCC = 4.5 V; -55oC to 125oC 7
Output Transition Time tTLH, tTHL 22 ns CL = 50pF; VCC = 4.5 V; -55oC to 125oC 7
Input Capacitance CI 10 pF CL = 50pF; -55oC to 125oC 7
DC Supply Voltage VCC -0.5 7 V 3
DC Input Diode Current IIK -20 20 mA For VI < -0.5 V or VI > VCC + 0.5 V 3
DC Output Diode Current IOK -20 20 mA For VO < -0.5 V or VO > VCC + 0.5 V 3
DC Drain Current, per Output IO -25 25 mA For -0.5 V < VO < VCC + 0.5 V 3
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5 V or VO < VCC + 0.5 V 3
DC VCC or Ground Current ICC -50 50 mA 3
Maximum Storage Temperature Range -65 150 oC 3
Maximum Junction Temperature 150 oC 3
Maximum Lead Temperature (Soldering 10s) 300 oC 10 s; SOIC - Lead Tips Only 3
Supply Voltage Range, VCC (HCT Types) VCC 4.5 5.5 V HCT types operation 1
Temperature Range, TA TA -55 125 oC 3
DC Input or Output Voltage VI, VO 0 V 0 V to VCC (maximum printed as VCC) 3
Input Rise and Fall Time 500 ns VCC = 4.5 V 3
Thermal Resistance, M (SOIC) Package θJA 73 oC/W Typical; package thermal impedance per JESD 51-7 (Note 1) 3

CAD (KiCad official)

  • Symbol: CD74HCT597M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct597m96-etched.step / cd74hct597m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct597m96.step / cd74hct597m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 e5266044e80e9078, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF