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CD74HCT4046AE

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT4046AE

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · PDIP-16

CD74HCT4046AE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PCPOUT output Phase comparator pulse output; the provided pages give no electrical limits for this pin.
2 PC1OUT output Phase comparator 1 output; PC1 is an Exclusive-OR network whose averaged output is fed to the VCO input through the low-pass filter.
3 COMPIN input Comparator input, which receives the VCO output either directly or through a frequency divider.
4 VCOOUT output VCO output with a specified duty factor of 50%, connectable directly to COMPIN or through a frequency divider.
5 INH input Inhibit input: a LOW level enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption.
6 C1A passive Connection A of external capacitor C1, which together with R1 determines the VCO frequency range.
7 C1B passive Connection B of external capacitor C1, connected between C1A and C1B.
8 GND power_in Ground (0 V) return for the device and for external resistor R1, R2 and the DEMOUT load resistor RS.
9 VCOIN input VCO input with high input impedance, which simplifies low-pass filter design.
10 DEMOUT output Demodulator output equal to the VCO input voltage; a load resistor RS to GND should be connected if used, otherwise it should be left open.
11 R1 passive Connection for external resistor R1 to GND, which together with C1 determines the VCO frequency range.
12 R2 passive Connection for external resistor R2 to GND, which enables a VCO frequency offset if required.
13 PC2OUT output Phase comparator 2 output; with no signal at SIGIN the PC2 loop adjusts the VCO to fMIN with VVCOIN = 0 V.
14 SIGIN input Self-biased signal input that can be directly coupled for signals within HC family logic levels, while smaller swings require capacitive coupling.
15 PC3OUT output Phase comparator 3 output; with no signal at SIGIN the PC3 loop adjusts the VCO to fMAX with VVCOIN = VCC.
16 VCC power_in Positive supply: 4.5 V to 5.5 V operation for HCT types, with the VCO section specified at 3 V to 6 V and the digital section at 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (HCT types) VCC 4.5 5.5 V HCT Types 6
Temperature range TA -55 125 °C 6
Input rise and fall time 500 ns VCC = 4.5V 6
R1 range (external resistor) R1 3 300 kΩ Application Information: recommended external component range 19
R2 range (external resistor) R2 3 300 kΩ Application Information: recommended external component range 19
R1 + R2 parallel value 2.7 kΩ Application Information: R1 + R2 parallel value 19
C1 capacitance (external) C1 40 pF Application Information: greater than 40pF 19
DC supply voltage VCC -0.5 7 V 6
DC input diode current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 6
DC output diode current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 6
DC drain current, per output IO -25 25 mA For -0.5V < VO < VCC + 0.5V 6
DC output source or sink current per output pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V 6
DC VCC or ground current ICC -50 50 mA 6
Maximum junction temperature 150 °C 6
Maximum storage temperature range -65 150 °C 6
Maximum lead temperature (soldering) 300 °C Soldering 10s 6

CAD (KiCad official)

  • Symbol: CD74HCT4046AE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct4046ae-etched.step / cd74hct4046ae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct4046ae.step / cd74hct4046ae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 13b9d2164822f9f0, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF