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CD74HCT21M96

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT21M96

Texas Instruments · Logic Gates · SOIC-14

CD74HCT21M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 input A of the 4-input AND gate (Y = A·B·C·D); TTL-compatible inputs with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
2 1B input Channel 1 input B of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
3 NC unconnected Not internally connected.
4 1C input Channel 1 input C of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
5 1D input Channel 1 input D of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
6 1Y output Channel 1 output Y, high only when all four inputs A, B, C and D are high; balanced CMOS push-pull output.
7 GND power_in Ground reference for the device; continuous current through VCC or GND is limited to ±50 mA (absolute maximum).
8 2Y output Channel 2 output Y, high only when all four inputs A, B, C and D are high; balanced CMOS push-pull output.
9 2A input Channel 2 input A of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
10 2B input Channel 2 input B of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
11 NC unconnected Not internally connected.
12 2C input Channel 2 input C of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
13 2D input Channel 2 input D of the 4-input AND gate; TTL-compatible input with VIL max 0.8 V and VIH min 2 V at VCC 4.5 V to 5.5 V.
14 VCC power_in Positive supply, recommended 4.5 V to 5.5 V (Section 6.3); each VCC pin should have a 0.1 µF bypass capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
Supply voltage VCC -0.5 7 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Input transition rise and fall time tt 500 ns VCC = 4.5 V 4
Input transition rise and fall time tt 400 ns VCC = 5.5 V 4
Operating free-air temperature TA -55 125 °C 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -25 25 mA VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Lead temperature (soldering) 300 °C soldering 10 s, SOIC lead tips only 4
Storage temperature Tstg -65 150 °C 4
High-level output voltage VOH 4.4 V VI = VIH, IOH = -20 µA, VCC = 4.5 V, TA = 25°C 5
High-level output voltage VOH 3.98 V VI = VIH, IOH = -4 mA, VCC = 4.5 V, TA = 25°C 5
High-level output voltage VOH 3.84 V VI = VIH, IOH = -4 mA, VCC = 4.5 V, TA = -40°C to 85°C 5
High-level output voltage VOH 3.7 V VI = VIH, IOH = -4 mA, VCC = 4.5 V, TA = -55°C to 125°C 5
Low-level output voltage VOL 0.1 V VI = VIL, IOL = 20 µA, VCC = 4.5 V, TA = 25°C 5
Low-level output voltage VOL 0.26 V VI = VIL, IOL = 4 mA, VCC = 4.5 V, TA = 25°C 5
Low-level output voltage VOL 0.33 V VI = VIL, IOL = 4 mA, VCC = 4.5 V, TA = -40°C to 85°C 5
Low-level output voltage VOL 0.4 V VI = VIL, IOL = 4 mA, VCC = 4.5 V, TA = -55°C to 125°C 5
Input leakage current II -0.1 0.1 µA VI = VCC and GND, IO = 0, VCC = 5.5 V, TA = 25°C 5
Input leakage current II -1 1 µA VI = VCC and GND, IO = 0, VCC = 5.5 V, TA = -40°C to 85°C 5
Supply current ICC 2 µA VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = 25°C 5
Supply current ICC 20 µA VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = -40°C to 85°C 5
Supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = -55°C to 125°C 5
Additional quiescent device current per input pin ΔICC 100 360 µA VI = VCC, 2.1 V, VCC = 4.5 V to 5.5 V, TA = 25°C 5
Additional quiescent device current per input pin ΔICC 450 µA VI = VCC, 2.1 V, VCC = 4.5 V to 5.5 V, TA = -40°C to 85°C 5
Additional quiescent device current per input pin ΔICC 490 µA VI = VCC, 2.1 V, VCC = 4.5 V to 5.5 V, TA = -55°C to 125°C 5
Input capacitance Ci 10 pF VCC = 5 V 5
Propagation delay A, B, C or D to Y tpd 27 ns CL = 50 pF, VCC = 4.5 V, TA = 25°C 5
Propagation delay A, B, C or D to Y tpd 34 ns CL = 50 pF, VCC = 4.5 V, TA = -40°C to 85°C 5
Propagation delay A, B, C or D to Y tpd 41 ns CL = 50 pF, VCC = 4.5 V, TA = -55°C to 125°C 5
Propagation delay A, B, C or D to Y tpd 11 ns CL = 15 pF, VCC = 5 V 5
Transition-time tt 15 ns CL = 50 pF, VCC = 4.5 V, TA = 25°C 5
Transition-time tt 19 ns CL = 50 pF, VCC = 4.5 V, TA = -40°C to 85°C 5
Transition-time tt 22 ns CL = 50 pF, VCC = 4.5 V, TA = -55°C to 125°C 5
Junction-to-ambient thermal resistance RθJA 102.3 °C/W D (SOIC) 14 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 58.7 °C/W D (SOIC) 14 pins 4
Junction-to-board thermal resistance RθJB 58.2 °C/W D (SOIC) 14 pins 4
Junction-to-top characterization parameter ΨJT 19.9 °C/W D (SOIC) 14 pins 5
Junction-to-board characterization parameter ΨJB 57.8 °C/W D (SOIC) 14 pins 5

CAD (KiCad official)

  • Symbol: CD74HCT21M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hct21m96-etched.step / cd74hct21m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct21m96.step / cd74hct21m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 11fe0afbe009c65b, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF